Verification capability is largely a matter of programming. VHDL is a capable programming language. Like SystemVerilog, writing directly in VHDL is tedious and potentially error prone. Open Source VHDL Verification Methodology™ (OSVVM™) is VHDL’s answer to SystemVerilog’s UVM.
OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, scripting API, and co-simulation capability that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC.
OSVVM supports the same capabilities that other verification languages support – from transaction level modeling, to functional coverage and randomized test generation, to data structures, and to basic utilities. The intention of OSVVM goes beyond capability though – OSVVM intends to make verification environments easy, readable, and fun.
Capabilities of OSVVM
OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that provide:
- A structured transaction-based verification framework using verification components.
- A common, shared transaction API for address bus (AXI4, Axi4Lite, Avalon, …) and streaming (AXI Stream, UART) verification components.
- Improved readability and reviewability by the whole team including software and system engineers.
- Improved reuse and reduced project schedules.
- Buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering that are simple to use and work like built-in language features.
- A common scripting API to run all simulators. OSVVM scripting supports GHDL, NVC, Aldec Riviera-PRO and ActiveHDL, Siemens Questa and ModelSim, Synopsys VCS, and Cadence Xcelium.
- Unmatched test reporting with HTML based test suite reports, test case reports, and logs that facilitate debug and test artifact collection.
- Support for continuous integration (CI/CD) with JUnit XML test suite reporting.
- A rival to the verification capabilities of SystemVerilog + UVM.
Looking to improve your VHDL verification methodology? OSVVM provides a complete solution for VHDL ASIC or FPGA verification. There is no new language to learn. It is simple, powerful, and concise. Each piece can be used separately. Hence, you can learn and adopt pieces as you need them.
OSVVM demonstrates that you can have capability, simplicity, readability, and conciseness all from one language and methodology.
In OSVVM we code our transaction based models using familiar entities and architectures. Hence, the coding of these models can be either behavioral or RTL-like. Generally this means that the models written by the testbench team are easily read by the RTL design team. It also means the RTL team can write testbench models.
All OSVVM features are created in the free, open-source library. No special licensing beyond a VHDL simulator that supports VHDL-2008.
OSVVM Simulator Support
OSVVM is supported on Aldec’s Riviera-PRO and Active-HDL, Siemen’s QuestaSim and ModelSim, Synopsys VCS, Cadence Xcelium, GHDL (open source), and NVC (open source) simulators.
OSVVM is maintained by volunteers. In addition to using this methodology, you can contribute by providing feedback to make it better.
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Already using OSVVM. We can arrange for you to share your OSVVM story in our Blog
OSVVM and “Open Source VHDL Verification Methodology” are trademarks of SynthWorks Design Inc.