Verification capability is largely a matter of programming. VHDL is a capable programming language. Like SystemVerilog, writing directly in VHDL is tedious and potentially error prone. Open Source VHDL Verification Methodology™ (OSVVM™) provides a methodology and library to simplify the entire verification effort. OSVVM supports the same capabilities that other verification languages support – from transaction level modeling, to functional coverage and randomized test generation, to data structures, and to basic utilities. The intention of OSVVM goes beyond capability though – OSVVM intends to make verification environments easy, readable, and fun.
Capabilities of OSVVM
OSVVM offers the same capabiities as those based on other verification languages.
- Transaction-Level Modeling
- Constrained Random test generation
- Functional Coverage with hooks for UCIS coverage database integration
- Intelligent Coverage Random test generation
- Utilities for testbench process synchronization
- Transcript files
- Error logging and reporting – Alerts and Affirmations
- Message filtering – Logs
- Scoreboards and FIFOs (data structures for verification)
- Memory models
OSVVM demonstrates that you can have capability, simplicity, readability, and conciseness all from one language and methodology.
In OSVVM we code our transaction based models using familiar entities and architectures. Hence, the coding of these models can be either behavioral or RTL-like. Generally this means that the models written by the testbench team are easily read by the RTL design team. It also means the RTL team can write testbench models.
All OSVVM features are created in the free, open-source library. No special licensing beyond a VHDL simulator that supports VHDL-2008.
OSVVM Simulator Support
Currently OSVVM is supported on Aldec, Mentor, and GHDL (open source) simulators. Additional simulator support announcements are expected in the near future.
OSVVM is maintained by volunteers. In addition to using this methodology, you can contribute by providing feedback to make it better.
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OSVVM and “Open Source VHDL Verification Methodology” are trademarks of SynthWorks Design Inc.