Abstract OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OS... »
OSVVM release 2021.10 focused on improving OSVVM’s reporting capability. In my last post, “OSVVM 2021.10: Build Summary Reports“, I talked about our HTML and JUnit CI reports that allow us to assess whether a set of tests have passed or quickly access which test cases failed. This post features OSVVM’s 2021.10 HTML based Functional Coverage reports. This has been in my mind... »
When we run a set of tests, we need to be able to assess whether all test cases passed or quickly identify which test cases failed. This is the purpose of the OSVVM 2021.10 Build Summary Reports. When tests fail, we need to have detailed information for each test case in a separate report that helps reveal the source of the issue. This is the purpose of the OSVVM 2021.10 Detailed Test Case Reports... »
In my earlier post I discussed how you could get around the pre-VHDL-2008 scoping rules by using external names, in this post we will look at using an external name to help us write an OSVVM functional coverage model for the Blackjack state machine shown in figure 1: The aim of our functional model is to create a coverage bin for each state transition so we can ensure that during our tests, every ... »
Webinar OSVVM: ASIC Level Verification, Simple Enough for FPGAs. Thursday October 5, 2017 Just because your design is complex does not mean your testbench needs to be. With Open Source VHDL Verification Methodology (OSVVM), we have found that with proper abstractions we can create simple, readable, and powerful testbenches – and we can even have some fun while doing it. OSVVM provides an ASI... »
Webinar OSVVM for VHDL Testbenches. Thursday June 25, 2015 Open Source VHDL Verification Methodology (OSVVM) is a comprehensive, advanced VHDL verification methodology. Like UVM, OSVVM is a library of free, open-source code (packages). OSVVM uses this library to implement functional coverage, constrained random tests, and Intelligent Coverage random tests with a conciseness, simplicity and capabil... »
Over the summer I have been working on the next set of revisions for OSVVM. One of the new features allows a name to be specified for each bin. The name is specified in calls to AddBins and AddCross. If a name is present, calls to WriteBin will print it. One motivation for a bin name is to correlate a requirement with it being tested (PASSED) or not tested (FAILED). Hence the output of WriteBin is... »
Webinar Thursday June 26, 2014 OSVVM provides functional coverage and randomization utilities that layer on top of your transaction level modeling (tlm) based VHDL testbench. Using these you can create either basic Constrained Random tests or more advanced Intelligent Coverage based Random tests. This simplified approach allows you to utilize advanced randomization techniques when you need them an... »
In a constrained random approach, different items can be selected more frequently by using randomization weights. Items with a higher randomization weight are selected more frequently. In Intelligent Coverage, the same effect can be achieved by using coverage goals. A coverage goal specifies how many times a value must land in a bin before the bin is considered covered. Each bin within the coverag... »