Abstract Small projects may use a single library for all aspects of the project. As projects increase in size separating different chips into separate VHDL libraries can help avoid naming conflicts. Libraries can also be used to separate different aspects of a project, such as separating the design from the testbench. As a language VHDL makes the usage of libraries easy. Unfortunately, many si... »
SynthWorks is continuing with our monthly instructor lead, on-line VHDL classes. With our “half day” on-line format, we do on-line classes right. Accelerate your learning pace of OSVVM. For additional class dates see: https://synthworks.com/public_vhdl_courses.htm We frequently arrange the lecture portion of the OSVVM classes in the early day for US so that our colleagues in Europ... »
In this second webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL’s protected type capabilities. Protected types simplify and abstract the construction of data structures. As such they are the enabling feature that makes it possible to create VHDL verification methodologies that are competitive with SystemVerilog + UVM, such as Open Source VHDL Verifi... »
IEEE 1076-2019, fondly referred to as VHDL-2019, was approved by IEEE RevCom in September 2019 and published in December 2019. The effort was supported mainly by VHDL users – from requirements definition to LRM writing. This is different from the past where employees of EDA vendors did much of the work – particularly the LRM writing. Language changes were use model driven and had multiple opportun... »
VHDL-93 (IEEE 1076-1993) created shared variables of an ordinary type as a temporary solution – which was noted in the standard document (aka LRM). VHDL-2000 (IEEE 1076-2000) created protected types as the only type to be used with shared variables and deprecated and removed the usage of a shared variable with an ordinary type. One of the places shared variables of an ordinary type are still use... »
Ever wanted to encapsulate all the signals of an interface (such as AXI4Lite, I2C, …) into a single record only to be confounded by not being able to specify the direction for the elements of the record? In this article we will explore how to do this with either VHDL-2019 interfaces or OSVVM interfaces. VHDL-2019 Interfaces Step 1: A Record is the foundation VHDL-2019 interfaces start with a recor... »
VHDL-2019 was approved by IEEE RevCom in September 2019 and published in December 2019. It was an effort supported mainly by VHDL users – from requirements definition to LRM writing. This is different from the past where employees of EDA vendors did much of the work – particularly the LRM writing. Language changes were use model driven and had multiple opportunities to be pruned from implementatio... »
There are many things that differentiate VHDL from Verilog. One example, is the ability to use global signals in Verilog, which enables a signal at the top-level to connect to one or more points in the hierarchy. This particular feature is used very effectively by Xilinx, to distribute the Global Set/Reset signal GSR to their IP and cell simulation models. The signal is generated in the glbl.v, wh... »
The IEEE P1076 VHDL Standards Working Group has been busy preparing VHDL-2017. It is almost ready. As we are wrapping up, it is time for the VHDL community to prepare to ballot (aka vote). Balloting on the standard will be done some time between May and July. If you are a member of the VHDL community, it is time to get ready to vote. Voting is done through IEEE. Directions are below. You have unti... »
Currently the IEEE P1076 Working group is reviewing a draft of the proposed IP Encryption (P1735) and accessing how it maps into the pragmas created in VHDL-2008. If you are developing and/or selling VHDL IP that you want to encrypt, you should be participating in this. More details at: https://www.eda.org/twiki/bin/view.cgi/P1076/ To participate, contact Jim at SynthWorks.com »