Introduction The OSVVM co-simulation environment has the ability to generate transactions from C++ to drive various virtual components (VCs), such as AxiBus, AxiStream, Ethernet, Uart, dual port RAM etc. But did you know that you can drive multiple VCs from within the same test bench, all driven by C++ software? To do this we have the concept of ‘nodes’. The OSVVM co-simulation documentation does ... »
Introduction In this article I want to give some thoughts on how to model interrupts within the OSVVM co-simulation environment. The manual details how to register an interrupt callback function with the software and this is called whenever the interrupt request input (IntReq) to the CoSimTrans VHDL procedure changes with the new state. This makes the interrupt request state available to the softw... »
When we run a set of tests, we need to be able to assess whether all test cases passed or quickly identify which test cases failed. This is the purpose of the OSVVM 2021.10 Build Summary Reports. When tests fail, we need to have detailed information for each test case in a separate report that helps reveal the source of the issue. This is the purpose of the OSVVM 2021.10 Detailed Test Case Reports... »
In reply to a LinkedIn post that regurgitated the old statement that VHDL is verbose, I replied, “With the VHDL-2008 update, Verilog is more verbose than VHDL.” This led my old friend Cliff Cummings and I to trade a few VHDL vs. System Verilog jabs. One of the things he brought up as concise SystemVerilog verification capabilities are singletons and verification data structures. Rather than give a... »