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2026.01 updates          

CoSim

• Adds CoSimPCIe Verification Component – Thanks to Simon Southwell

 
MIT – DoDirectiveTransactions

• Added DoDirectiveTransactions (AddressBus and Stream) to implement common directive transactions

 
VHDL-2019 Interface

• Added VHDL-2019 interface capability to AddressBus and Axi4 Full VC
• Support for interfaces in Stream deferred to later revision due to vendor support issues in many simulators.

 
AXI4 Full VC

• Added VHDL-2019 interfaces
• Architectures are now separate from the entity in Axi4Manager_a.vhd, Axi4Subordinate_a.vhd, and Axi4Memory_a.vhd
• If you need to update architectures, only update the 2019 architecture (in src) and enable TCL variable OsvvmDevDeriveArchitectures “true” in OsvvmSettingsLocal.tcl

 
ScoreboardGenericPkg

• Updated FindAndFlush and FindAndDelete s.t. if the item is found, it reports as a PASSED and otherwise as FAILED

 
Opening VHDL Test Case File

• Opening VHDL Test Case File in vscode, in OsvvmSettingsLocal.tcl set:
  variable VhdlFileViewerPrefix "vscode://file/" ;
  • Default, view in browser
  • Assumption, test case file is the one compiled just before simulate

Test Case Alert Reports

• For VHDL-2019 simulators, integrate VHDL Assert counts into test pass/fail and Alert reporting (AlertLogPkg)

 
Language Support Package

• Added Constant: TOOL_USES_32_BIT_INTEGERS

 
Updated build error handling

• By default OSVVM catches all errors and ending with a Tcl error is off.
• This is desirable as when running CI, you want all test cases that can run to run.
• When running CI, use the JUnit test reporter to generate pass/fail messages
• Add the following tcl variables to your OsvvmSettingsLocal.tcl to adjust TCL error signaling:
  • FailOnBuildErrors – Signal a tcl error if an error was signaled during a build. Default is false.
  • FailOnReportErrors -Signal a tcl error if an error was signaled during reporting. Default is false.
  • FailOnTestCaseErrors – Signal a tcl error any test case fails during a build. Default is false.
  • AnalyzeErrorStopCount – if 0, do not signal Analyze errors, otherwise, signal analyze error (and stop) when AnalyzeErrorStopCount errors occur. Default is 0.*
  • SimulateErrorStopCount – if 0, do not signal Simulate errors, otherwise, signal simulate error (and stop) when SimulateErrorStopCount errors occur. Default is 0*
• If you have errors in any part of the OSVVM process, adjust the following TCL variables
  • TclDebug – When true and an OSVVM API command fails, print Tcl’s $::errorInfo when an error occurs. Default false.
  • ReportDebug – When true and OSVVM reporting fails, print Tcl’s $::errorInfo when an error occurs. Default false.

 
Note: SetInteractiveMode will change both AnalyzeErrorCount and SimulateErrorCount to 1 and Debug to true (which the same impact as TclDebug).

 
Build Summary Report Updates

• If TestSuite has 0, 0, 0 => status is EMPTY
• If analyze fails before simulate, test case will FAIL and report Analyze Failed
• If simulate is run interactively, it runs like a build and produces a build report linked into the Index of Builds.

 
Compile Lists as TOML and CSV List

• CreateDryRunDict – Instead of running analyze and simulate, collect file list and simulate list as dictionaries.
• CreateAnalyzeListCsv – Run in DryRun and produce a inorder CSV list of files
  • Closes OSVVM/OSVVM-Scripts#62
• CreateVhdlLsToml – Run in DryRun and produce VHDL LS Toml files.
  • Closes OSVVM/OSVVM-Scripts#72

 
Scripts & 2019 Features

• Added VHDL-2019 feature controls. These are set automatically in the VendorScripts_***.tcl file.
• SetVHDLVersion 2019 automatically done for tools that support it.
  • Turn off by doing SetVHDLVersion 2008 in your OsvvmSettingsLocal.tcl

 
Report Stuff

• Yaml updates to better collaborate with https://github.com/edaa-org/pyEDAA.OSVVM

 
SPI

• Updated SPI test suite so that it is passing again

 
 

• no wlf data after build in Questa
• Script opens new instance of Questa causing license issue

In 2025.06 the following has been updated:

Build Directories

• All build output is now collected into a build directory
• Default name: DirName_ScriptName
• Set the name with BuildName in the *.pro file

Index of Builds

• Summary of each build run is kept in index.html
• Index.html tracks pass/fail of each build as well as time a build takes.

Tcl procedure CreateTestCaseCommonPkg

• Creates a constant, PATH_TO_VALIDATED_RESULTS, to locate the validated results directory.

Tcl procedure RunAllTests

• Select tests to run using a pattern
• Allows semi-autonomous running of tests

Questa – new vs. old script flows

• New script flow simulates using vopt + vsim flow – uses VendorScripts_Questa.tcl (recommended by Siemens)
• Old script flow simulates using vsim – uses VendorScripts_Siemens.tcl
• OSVVM 2025.06 selects the new script flow for Questa 2025.2 and newer
• Older versions of OSVVM and Questa select old script flow
• Select the script flow you want by setting OSVVM_TOOL environment variable to Questa (new) and Siemens (old)

Clock edge specification for WaitForClock and WaitForTransaction

• ClkActive parameter now allows ‘1’ (rising edge), ‘0’ (falling edge), ‘-‘ (any edge)

Most VC Test Cases updated to

• Use CreateTestCaseCommonPkg to find the PATH_TO_VALIDATED_RESULTS
• Use TranscriptOpen without a parameter
• Use EndOfTestReports with TIMEOUT and NOCHECKS detection

• Wishbone – Added Wishbone with a manager and subordinate VC
• Scripts
  • Generic names that include paths now make file names without the : and /
  • Updated how Settings Directory gets located
  • For Siemens, turned off VHDL-2019 settings as release 2025.1 claims it is not supported
• Updated documentation
  • AXI4 and AxiStream now includes using Delay Coverage
  • CoveragePkg user guide – includes NewReqID
  • OsvvmSettings user guide
  • DelayCoveragePkg user guide

• Xilinx XSIM – With this update, XSIM 2024.2 supports OSVVM
• Requirements Tracking now tracks requirements expressed as functional coverage
• Settings

• Documentation – caught up to current version
• RandomPkg/RandomPkg2019 – added scalar exclude values
• DelayCoverage – added SetBurstLength. Updated SetDelayCoverage to randomize BurstLength
• NVC – added CoverageVendorApiPkg_NVC.vhd to couple OSVVM’s functional coverage to NVC – Thanks to Ondrej for the pull request
• AddressBus MIT – added WriteBurstVector and CheckBurstVector for integer_vector
• Updated html log files to better handle details tags
• Updated scripts to better handle spaces in path

2024.11a release addresses issues with files in osvvm/deprecated directory:

• LanguageSupport2019Pkg_c.vhd – to_string for integer_vector (stand in for VHDL-2019 feature), only handled ranges 1 to Length – this impacts usage of ScoreboardPkg_IntV and AffirmIfEqual for integer_vector.
• FileLinePathPkg_c.vhd – missing return statements in place holder functions. They are currently unused so there was no impact other than compile warning messages.

• OSVVM Utility Library (OSVVM)
  • Added RandomPkg2019 – supports randomization without protected types
  • ScoreboardGenericPkg – Added FindAndDelete, FindAndFlush. Updated data structure.
  • AlertLogPkg – Added AffirmIfFilesMatch. Updated AffirmIfTranscriptsMatch. Both support IgnoreSpaces and IgnoreEmptyLines
  • TbUtilPkg – Added predefined barriers in record PredefinedBarrierType. Names introduced in 2024.07 are now aliases to the record.
• Scripts – Turned on VHDL-2019 compilation is supported if the version is as below
  • NVC: Version >= 1.13.2
  • Riviera-PRO: Version >= 2021.04
  • Active-HDL: Version >= 12.0
  • Questa: Version >= 2024.2
• AXI4 Family (library AXI4)
  • AXI4 – Added Axi4GenericSignalsPkg and testbench_GenericSignals
  • AxiStream – Updated AxiStreamGenericSignalsPkg and added testbench_GenericSignals
  • Axi4InterfacePkg- Added Axi4RecArrayType. Made Axi4RecType a type rather than an alias

• Breaking changes in Test Status and CreateClock
  • To maintain backward compabitility, set the script variable OsvvmVersionCompatibility to a value 2024.05 or less in OsvvmSettingsLocal.tcl.
  • OSVVM provides OsvvmSettingsLocal_example.tcl that can be used to create your OsvvmSettingsLocal.tcl
  • AlertLogPkg and TbUtilPkg below show individual ways to override these.
  • Note however, if you used selected paths to these procedures, it is a breaking change as the paths have changed from “OSVVM.TbUtilPkg.CreateClock” to “OSVVM.CreateClockPkg.CreateClock”
  • Note there are also breaking changes related to TbUtilPkg and named association of Polarity input. See TbUtilPkg below for details.
• AlertLogPkg
  • Test Status now reports as: PASSED, FAILED, NOCHECKS, TIMEOUT.
  • By default status NOCHECKS is FAILED. Set script variable FailOnNoChecks to false in OsvvmSettingsLocal.tcl to make it PASSED (old behavior)
  • PathTail now adds generate label to the name it creates.
• TbUtilPkg
  • Added predefined barrier signals: OsvvmTestInit, OsvvmResetDone, OsvvmTestDone, TestDone, OsvvmVcInit
  • All procedures that have a Clk input now have a ClkActive input
  • The polarity input on procedures has changed name to differentiate it from ClkActive. Expected impact is minimal. Named association calls will need to be updated with the new name. Procedures impacted: WaitForTransaction, WaitForTransactionOrIrq, WaitForBarrier(2), WaitForClock, WaitForLevel
  • Moved CreateClock and CreateReset and friends from TbUtilPkg to ClockResetPkg
• CoveragePkg: Coverage models with Coverage Weight of 0 print last and are hidden in the html by default
• MemoryGenericPkg
  • Throws Errors on AddrWidth > 40 and warnings if AddrWidth > 36.
  • With the Error message, AddrWidth is truncated to 40 and the memory tries to operate.
  • Note some simulators die even at AddrWidth = 36.
  • Thanks to those reported tool crashes without warnings.
• ClockResetPkg
  • Updated CreateClock with Offset, ClkActive, and Enable . Clock starts with ClkActive value after the Offset. At startup it has the initial signal value if set, otherwise, not ClkActive (if Offset > 0 sec).
  • Old version of create clock is available as OldCreateClock. Its startup behavior is slightly different.
  • Old version of create clock is available as CreateClock when ClockResetVersion is set to 2024.05 or less in OsvvmSettingsLocal.tcl.
    New versions will not be available though.
  • Added CreateJitterClock whose jitter is controlled by a coverage model
  • Thanks to those who continued asking about an upgrade to CreateClock
• ScoreboardPkg
  • Made all generic functions impure
  • Added scoreboards for unsigned, signed, and integer_vector (IntV)
• ReportPkg
  • Added TimeOut input to EndOfTestReports
  • Added scoreboard reporting for: unsigned, signed, and integer_vector (IntV)
• Scripts
  • Include now has better error handling and restoration of state
  • Updated support for Synopsys VCS, Cadence Xcelium, and added support for Siemens Visualizer
  • Fixed DoWaves for Aldec. Fixed SetLogEnable.
• AXI4
  • Shortened AlertLogID Names to improve reports
  • AxiStreamReceiver – Added OsvvmVcInit to support setting of WaitForGet before TReady is active.
• UART: Minor updates to work around tool issues (Synopsys VCS and Cadence Xcelium).
• Regressions run on
  • GHDL 4.1.0. Latest release run on GitHub Actions
  • NVC 1.13.0
  • Aldec RivieraPRO 2023.10
  • Aldec ActiveHDL 14
  • Aldec VSimSA 14 (related to ActiveHDL)
  • Siemens Questa 2024.02_1.
  • Siemens Visualizer 2024.02_1 runs and individual tests pass, but hangs when running a large number of test cases
  • Synopsys VCS V-2023.12-SP2
  • Cadence Xcelium 2024.03 – passes osvvm library internal tests, but does not pass the OSVVM public tests (for OSVVM VC)
  • Xilinx XSIM 2024.1 – passes osvvm library internal tests, but does not pass the OSVVM public tests (for OSVVM VC)

• Updates to reports – YAML, HTML, and JUnit XML
• SPI VC Additions

• Settings/Configuration Updates
• Xilinx Update
• OSVVM Issues Resolved
• Added Verification Components
• Minor Updates

For more details see the OSVVM 2024.03 Release blog post.

The 2023.09 release adds:

• Scripts: build/include now support
  • Early detection of file or path not found and better error messages.
  • $::ARGV (a TCL array) and $::ARGC
  • $::argv (a TCL list), $::argc and $::argv0
• OsvvmSettingsPkg: Package with deferred constants to configure OSVVM settings.
  • RandomPkg – Provides the default value for InitSeed UseNewSeedMethods.
  • AlertLogPkg – Provides the default value for Justify and Print Time First for Alerts and Logs.
  • CoveragePkg – Provides the default value for Weight Mode (AT_LEAST or REMAIN).
• AlertLogPkg and ScoreboardPkg: Updated printing of messages (Alerts and Logs).
• ModelParametersSingletonPkg – implements a singleton for ModelParameters.
• Transaction Interface (Stream and AddressBus)
  • Added ModelParametersIdType to Transaction Interface to simplify parameter handling in VC.
  • Added ClassifyUnimplementedOperation to simplify and unify unimplemented transaction messages
  • Added extension operations EXTEND_* to allow VC to add custom options
  • Stream: Added SendAndGet and SendAndGetBurst transaction API calls
• ScoreboardGenericPkg – Added WriteScoreboardYaml parameters to allow simplification of names

• AlertLogPkg: Added WriteRequirementsYaml to write requirements for a test case into a YAML file
• ReportPkg: In EndOfTestReports if GotRequirements it calls WriteRequirementsYaml. Hence saving requirements is automatic.
• Scripts: For each test suite, merges the requirements yaml files for each test case and produces a test suite requirements HTML
• Scripts: For each build, merges the requirements yaml files for each test suite and produces a build requirements HTML and CSV
• If requirements are used, EndOfTestReports + OSVVM Scripts makes producing requirements HTML and CSV automatic.
• Scripts: Updated HTML for Build Summary and Test Case Summary outputs
• DpRam: Added burst support – thanks to Louis Adriaens for the pull request

• Co-simulation updates
  • Added split transaction methods for address bus model independent manager
  • Added support address bus model independent subordinate/responder
  • Added support for streaming bus model independent transactions
  • Added test data pattern generation methods
  • Added data check methods
• AxiStreamTransmitter and AxiStreamReceiver VC: Randomize delays for TValid and TReady
• Axi4Manager, Axi4Memory, and Axi4Subordinate VC: Randomize delays for XxValid and XxReady
• DelayCoveragePkg: New package that implements a pattern for randomizing cycle based delays such as AXI’s Valid and Ready.
• Documentation: Added DelayCoveragePkg_user_guide.pdf.
• OsvvmContext: Added DelayCoveragePkg.
• StreamTransactionPkg
  • Added transactions to SetUseRandomDelays, SetDelayCoverageID, GetDelayCoverageID
  • Added overloading for SendBurstVector[Async] and [Try]CheckBurstVector to use integer_vector
• AddressBusTransactionPkg added transactions to SetUseRandomDelays, SetDelayCoverageID, GetDelayCoverageID
• FifoFillPkg_slv added CheckBurstFifo
• CoveragePkg
  • Updated InitSeed to include name of ParentID – will cause differences in randomization
  • Added IsNotCovered
• AlertLogPkg: Bug fix in Yaml file. No longer has items whose ReportMode is DISABLED.
• ScoreboardGenericPkg: If a pop fails due to FIFO/Scoreboard empty, the error message will print the tag if it is used.
• Ethernet, Bug Fix: updated receivers to use repeat until loop instead of while loop to avoid issues with using old value in first check of loop
• DpRamController_Blocking.vhd, Bug Fix: Added LocalAddress to hold address so read operation logs correct address

• Updated co-simulation environment to support both Streaming Interfaces as well as Address Bus Interfaces.
• Script settings are now split between OsvvmScriptSettings.vhd which has deferred constants and a generated package body OsvvmScriptSettings_Generated.vhd (which is in the .gitignore) – Thanks Philip
• Updated Interrupt Handler to handle an array of interrupts.
• Fixed bug in Ethernet related to enables – Thanks Simon
• Fixed bug in Peek with a Tag – Thanks Tim
• Fixed bug in UART in generating a checking break during no parity mode – Thanks Bruce

• Co-simulation environment supports running software (C++) in a hardware simulation environment.
• Added OsvvmScriptSettings.vhd to the OSVVM utility library.
  • Autogenerated when the OSVVM library is analyzed.
  • Script settings with the OSVVM library
• Added Interrupt generator and updated interrupt handling.
• Added PassThru VC for Axi4, Axi4Lite, and AxiStream to act as the DUT in the OSVVM testbench environment.

• Updated StartUp.tcl to use OSVVM_TOOL environment variable to determine which tool is run when none is found
• Updated scripts for Synopsys VCS and Cadence Xcelium
• Updated log file creation to first use OsvvmBuild.log and then it is copied to “LogFileDirectory”/”BuildName”.log. This allows redirection (or tee) to OsvvmBuild.log to be used if other means of logging are not supported.
• Updated Generic Handling
  • Both Simulate and RunTest support calling generic
  • HTML log files link to generic tests properly
  • Transcripts for tests with generics have the generic information appended to the file name
• Refactored OSVVM reporting so it only depends on static OSVVM information
  • Allows scripts Report2Html, Report2Junit, Simulate2Html, and Log2Osvvm to be run separately
  • In tclsh, start the reporting environment by “source path_to_osvvm/OsvvmLibraries/Scripts/StartUpReports.tcl”
  • Added “SetTransactionType none” which turns off linking to OSVVM HTML log files

• Updated the Multiple Verification Component Test Example (UART/testbench_multiple_uarts)
• Defined array types for transactions: AddressBusRecArrayType and StreamRecArrayType
• Created AddressBus and Stream transactions that support indexing arrays of verification components
• Moved the InterruptHandler example to OsvvmLibrariesCommon/TbInterrupt and added InterruptHandler user guide to the documentation repository
• Scripts now generate Scoreboard reports for user defined scoreboards – See WriteScoreboardYaml in Scoreboard user guide.
• Scripts: TestName deprecates TestCase – coordinates with SetTestName
• Updated default search to PRIVATE_NAME for Scoreboard / FIFO, Coverage, and Memory data structures

• Added Ethernet Phy and MAC verification components for GMII, RGMII, MII, RMII
• Added interrupt handler that supports any verification component that uses the Address Bus Model Independent Interface
• RandomPkg: added SetRandomSalt as a method to add an offset to all InitSeed calculations – Thanks Torsten M
• Added demo of using generate with OSVVM VC in UART/testbench_multiple_uarts
• Scripts: HTML log files now flag errors in red outside of the hidden regions
• Scripts: Added DoWaves for adding additional waveform files to simulate – Thanks Anna
• Scripts: Added ChangeWorkingDirectory and JoinWorkingDirectory – Thanks @fhuemer
• Scripts: Ignore errors in wave.do + ignore it during batch sims – Thanks Markus
• NVC: Added support for NVC (open source simulator) – Thanks Adam
• GHDL: fixed transcript files (missing analyze and simulate outputs)
• GHDL: fixed generic – the script to set generics during simulate
• AlertLogPkg: SetTestName replaces SetAlertLogName

• Scoreboard Reports now done in a single table with one row per Scoreboard/FIFO
• Added RemoveLibrary, RemoveLibraryDirectory, and updated RemoveAllLibraries
• Added SetInteractiveMode, SetDebugMode, SetLogSignals – all default to FALSE for faster simulations
• Scripts now support callbacks to simplify user level customization
• For GHDL, added SetSaveWaves, SetExtendedElaborateOptions, SetExtendedRunOptions
• Default for TestSuite is now the library name (rather than Default)
• Updated CoverageEnable to “and” with CoverageAnalyzeEnable and CoverageSimulateEnable.

Note: The scripts for Aldec’s VSimSA (ActiveHDL batch version) are broken in this release.

• MemoryPkg now supports data words of any width
  • MemoryPkg stores data and X’s
  • MemoryPkg_NoX stores only data. X’s are mapped to 0.
• Analyze for Verilog now creates the library list, “-l lib1 -l lib2”
• Simulate supports two tops.
  • One time: simulate “design1 lib2.design2”
  • Many times: SetSecondSimulationTopLevel lib2.design2
• AlertLogPkg now uses SetOsvvmDefaultTimeUnits(ns) to print time values

The 2022.06 release adds:

• At build completion, print single-line, text-based build summary
• For CI, variable settings for failing on test errors.
• Updated HTML log file generation. Log file always created. HTML optionally created
• Optional generation of a do file – for submitting bug reports to vendors
• AlertLogPkg now has a output formatter that allows printing time first.
• CoveragePkg now propagates Pass Fail information to html reports.

The 2022.05c release updates AxiStreamReceiver and AxiStreamReceiverVti to fix an issue with reading the RECEIVE_READY_WAIT_FOR_GET parameter.

The 2022.05b release revises scripts to fix an issue when there are spaces in a library path.

The 2022.05a release revises scripts so that tools with older TCL revisions are still supported.

The 2022.05 release adds:

• Updated error handling in simulation scripts
• Reporting any analyze and simulate errors in the build summary report
• Linking to log file (log or html based) in the build summary report
• Updated all VC to have MODEL_ID_NAME and FIFOs with Search => PRIVATE.
  Ensures that VC have unique name and unique FIFOs when in generate loop.

• Axi4Memory Read Burst Data updated to add delay between each data word read
• Added Documents: OSVVM_Overview
• Updated all documentation and README files
• Added osvvm.github.io

• Added links to transcript files added during a test via TranscriptOpen
• Axi4 Lite updated to resolve all GHDL issues
• AxiStream updated so that a burst may use multiple calls to SendBurst
• TbUtilPkg added EdgeRose, EdgeFell, EdgeActive, FindRisingEdge, FindFallingEdge, FindActiveEdge
• Added documents, OSVVM’s Structured Testbench FrameWork and OSVVM’s Verification Component Developer’s Guide

• Log (transcript) files can be either html or text (log)
• Scoreboard reports are now included in the test detailed reports
• Link to simulation transcript output now included in test detailed reports
• Scripts optionally activate code coverage and simplify code coverage collection, merging, and reporting (html).
• Code coverage reports, when generated, are linked into the OSVVM html build reports.

• Burst Patterns (Vector, Incrementing, and Random) to Address Bus and Stream Model Independent Transactions.
• Formalized OSVVM’s Transition Coverage (TCover).
• Library directories are now lower case. Be sure to remove old libraries and recompile.

• Added ReadCovYaml to CoveragePkg.
• Updated library handling in scripts.
• Updated paths handling for analyze to relative paths.

• Minor updates to OSVVM’s Build Summary Reports in YAML, HTML, and JUnit XML
• Minor updates to Test detailed reports with Alert Information for each AlertLogID
• Minor updates to Test detailed reports with Functional Coverage Model information for each coverage model defined in the test

• Build Summary Reports in YAML, HTML, and JUnit XML
• Test detailed reports with Alert Information for each AlertLogID
• Test detailed reports with Functional Coverage Model information for each coverage model defined in the test

• • Scripting and code updates for Synopsys VCS.
  • Scripting and code updates for Cadence Xcelium
  • Updated AXI4 verification component names to match new names.
  • Updated AlertLogPkg and Scripts to support YAML test suite completion files
  • Updated testbenches to generate YAML test suite completion files

• CoveragePkg updated to use new data structures to simplify usage.
• CoveragePkg, ScoreboardGenericPkg, and MemoryPkg now all have a conventional call API.
• Except for RandomPkg, users no longer need to directly interact with protected types.
• Documentation and quick reference cards have been updated.
• Older protected type use models still supported, however, we recommended the new API for new testbenches.

The new data structure used by CoveragePkg, MemoryPkg, and ScoreboardGenericPkg creates a dynamic array of objects. The objects are Coverage Models, Memory Models, and Scoreboards/FIFOs. Protected types are still used, they are just hidden from the user. A similar data structure is used in AlertLogPkg. Having used AlertLogPkg since 2015, it makes me wonder why we did not do this for CoveragePkg, MemoryPkg, and ScoreboardGenericPkg sooner.

• OSVVM Utility updated data structures to simplify usage.
• OSVVM RandomPkg updated InitSeed for better seed creation. Selects old seed methods by default.
• Scripts updated to better support GHDL.
• AXI4 Full and AxiStream updated burst data structures for better capability and better support of GHDL.
• Axi4Memory updated to new memory data structure to simplify creation of ZYNQ models.
• GHDL now fully supported for scripts, OSVVM Utility, AXI4 Full, AxiStream, and UART.
• Usage of bursting in AXI4 Full and AxiStream has changed. See testbenches for details for now – both TestCtrl_e.vhd as well as TestCases. Otherwise, maintains full compatibility with previous versions.

• Refactored Scripts to better support Aldec’s Active-HDL
• In AXI4 and AxiStream components added Valid Delays
• Added Multiple driver detection
• Added New RequestTransaction/WaitForTransaction to support integer

• Virtual Transaction Interfaces.
• Word Burst mode to Axi4Master (Full) Verification Component.
• Documentation for Axi4 Verification components.
• Burst modes to the Address Bus Model Independent Transactions (MIT).

Release 2020.12a

• Fixes a SEGV Fatal in QuestaSim.

• Added Bursting to AxiStream Verification components.
• Created documentation for AxiStream Verification components.
• Added bursting to the Stream Model Independent Transactions (MIT).
• Updated UART for consistency with AxiStream and Stream MIT
• Added MetaMatch to ScoreboardPkg_slv, AlertIfEqual, AlertIfNotEqual