|March 31, 2014 at 22:35 #784|
Hi. I’m working on this 32-bit kogge stone adder and I can’t seem to get the wavform testbench right. The output signals are giving me H’UUUUUUUU and i cant seem to figure out the solution.
my testbench is as follows:
ENTITY testbench IS
ARCHITECTURE testbench_arch OF testbench IS
SIGNAL A : std_logic_vector (31 DownTo 0) := “00000000000000000000000000000000″;
constant PERIOD : time := 200 ns;
PROCESS — clock process for Cin
A <= “00000000000000000000000000000011″;
WAIT FOR 520 ns;
|April 2, 2014 at 09:03 #788|
I don’t see anything on OSVVM in your question, so it is probably better to ask these sort of things on Stack Overflow.
I don’t see anything obvious wrong with your testbench. Are the inputs getting to the design correctly? If they are then it is a matter of debugging your design – not your testbench.
To debug your design, use the simulator to view waveforms that are internal to your design. Use breakpoints to look at how a process runs. Breakpoints are easy. Bring up the code you are interested in looking at in your simulator. Select on the left side of a line to set a break point – a large dot should appear before the line. Some lines are not executable, so you cannot set a breakpoint there.
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