Vhdl test bench U Output

[hby01]

Hi. I’m working on this 32-bit kogge stone adder and I can’t seem to get the wavform testbench right. The output signals are giving me H’UUUUUUUU and i cant seem to figure out the solution.

my testbench is as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS “results.txt”;

COMPONENT ksa
PORT (
A : In std_logic_vector (31 DownTo 0);
B : In std_logic_vector (31 DownTo 0);
Cin : In std_logic;
Cout : Out std_logic;
Sum : Out std_logic_vector (31 DownTo 0)
);
END COMPONENT;

SIGNAL A : std_logic_vector (31 DownTo 0) := “00000000000000000000000000000000”;
SIGNAL B : std_logic_vector (31 DownTo 0) := “00000000000000000000000000000000”;
SIGNAL Cin : std_logic := ‘0’;
SIGNAL Cout : std_logic := ‘0’;
SIGNAL Sum : std_logic_vector (31 DownTo 0) := “00000000000000000000000000000000”;

constant PERIOD : time := 200 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 100 ns;

BEGIN
UUT : ksa
PORT MAP (
A => A,
B => B,
Cin => Cin,
Cout => Cout,
Sum => Sum
);

PROCESS — clock process for Cin
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
Cin <= ‘0’;
WAIT FOR (PERIOD – (PERIOD * DUTY_CYCLE));
Cin <= ‘1’;
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;

PROCESS
BEGIN
— ————- Current Time: 120ns
WAIT FOR 120 ns;
A <= “00000000000000000000000000000001”;
B <= “00000000000000000000000000010011”; 
— ————————————-
— ————- Current Time: 160ns
WAIT FOR 40 ns;
A <= “00000000000000000000000000000001”;
B <= “00000000000000000000000000010010”; 
— ————————————-
— ————- Current Time: 200ns
WAIT FOR 40 ns;
A <= “00000000000000000000000000000001”;
B <= “00000000000000000000000000000010”;
— ————————————-
— ————- Current Time: 240ns
WAIT FOR 40 ns;

A <= “00000000000000000000000000000011”;
B <= “00000000000000000000000000000010”;

WAIT FOR 520 ns;

END PROCESS;

END testbench_arch;

[Jim Lewis]

I don’t see anything on OSVVM in your question, so it is probably better to ask these sort of things on Stack Overflow.

I don’t see anything obvious wrong with your testbench.  Are the inputs getting to the design correctly?  If they are then it is a matter of debugging your design – not your testbench. 

To debug your design, use the simulator to view waveforms that are internal to your design.  Use breakpoints to look at how a process runs.  Breakpoints are easy.  Bring up the code you are interested in looking at in your simulator.  Select on the left side of a line to set a break point – a large dot should appear before the line.  Some lines are not executable, so you cannot set a breakpoint there.

[Author]

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