Reply To: Can OSVVM Verification Component be used in VUnit based testbench?

[Jim Lewis]

OSVVM connects the transaction interface (a signal of a record type) directly connects the test sequencer (our examples use the name TestCtrl) to the verification component – each have ports of the same type – AddressBusRecType for MM/address bus type interfaces. All the information is passed in the record data structure – with dedicated fields for things like address, data, and configuration values.

So just like your RTL, a specific signal connects the test sequencer to a specific VC.

Currently for single cycle accesses we do:
Write(Mm1Rec, Addr, X"AA") ;

For bursts we support a number of mechanisms, such as:
WriteBurstVector(Mm1Rec, Addr, (X"AA", X"BB", X"CC", X"DD") ) ;

This is actually a short hand for:

PushBurstVecctor(Mm1Rec.WriteBurstFifo, (X"AA", X"BB", X"CC", X"DD") ) ;
WriteBurst(Mm1Rec, Addr, 4) ; 

OSVVM BurstFifos for AXI4 can be configured to either transfer words (defined by the interface width) or bytes (which are then accumulated into the interface data width).

For more information on OSVVM transactions see the Address_Bus_Model_Independent_Transactions_user_guide.pdf in the OsvvmLibraries/Documentation directory. Alternately you can do a see OsvvmLibraries/AXI4/Axi4/TestCases and search for the word Burst.