OSVVM release 2024.07 + Conference Trip Report

It seems like yesterday that I got back from Verification Futures Conference (June 18) and FPGA Conference Europe (July 2-4) – but it is actually been three weeks now. A big part of that is because as soon as I got back, I have been focused on the OSVVM 2024.07 release – and I tend to get tunnel vision.

Verification Futures Conference – June 18

On June 18th I presented Essential Steps to Simplify VHDL Testbenches Using OSVVM to a community of 30 attendees. This was a great warm up for FPGA Conference Europe.

Vacation Ireland

After the conference, my wife and I took vacation in Ireland. We both drove a rental car in Ireland and learned that while in the US we drive on the right side of the road, in Ireland (and UK) they drive on the right side of the car – it is all about perspective.

The roads in Ireland redefine what is meant by narrow road. In Ireland, on a narrow road, bushes may touch both sides of the car – and you pass at pull outs (such as a driveway). Do get full car insurance as the car may get scratched – worth it – we paid for it by getting a manual – was not sure about shifting left handed, but it came naturally.

After Ireland, we slowly made our way to Munich via London and Brussels on a train – for me a very relaxing and productive way to travel. Pro tip, if you are changing trains in Frankfort, Germany, look into if you can change trains at the airport rather than the main station. Our train was running late and at the airport both trains used the same platform – where as in the city it would have been a hustle to make the connection.

FPGA Conference Europe – July 2 to 4

At FPGA Conference Europe I presented two regular papers and two tutorial length sessions:

• Paper: Why Should Our Team be Using VHDL+OSVVM for Verification
• Tutorial: Essential Steps to Simplify VHDL Testbenches Using OSVVM
• Tutoral: Using OSVVM’s AXI4 VC
• Paper: The Things I Hate about VHDL

The thing I love about FPGA Conference Europe is that the presentation rooms were filled to capacity (80+ for papers and 40+ for Tutorials) with additional people standing or sitting on the floor. It was wonderful to get the great feedback about how OSVVM is working for verification teams.

Thanks for PLC2 and Vogel for organizing the conference. Thanks to AMD for sponsoring the evening event at Motorworld Inn in Munich.

Why Should Our Team be Using VHDL+OSVVM for Verification (40 minute presentation)

This is a high level presentation that identifies the key aspects of a modern verification methodology and shows how to achieve them with OSVVM. A great paper to share with your management about why OSVVM (and OSVVM training) is important for your team.

Essential Steps to Simplify VHDL Testbenches Using OSVVM (90 minute tutorial presentation)

An engineers “Getting Started” presentation on the first, essential steps you need to make when looking to improve your VHDL testbench approach. We examine OSVVM’s approach to transaction-based testing, self-checking tests, constrained random tests, scoreboards, functional coverage, messaging, error handling, specification tracking, scripts, and test reports (HTML and Junit).

Using OSVVM’s AXI4 VC (90 minute tutorial presentation)

An engineers “Getting Started” presentation on how to use the OSVVM AXI4 verification components in your testbenches.

The Things I Hate about VHDL (40 minute presentation)

This presentation identifies some of the negative things we hear about VHDL – like it is too verbose, strong typing is horrible, VHDL is like assembly language, instead we need a higher level language like C, … – and shows how they have either already been fixed or are non-sense. If you have a VHDL wish list or proposal, share it with the IEEE VHDL WG at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/.

OSVVM Release 2024.07

When I got home on July 6th, it was time complete the on-going work on the 2024.07 OSVVM release. A highlight of updates include:

• Tests now report status as: PASSED, FAILED, NOCHECKS, and TIMEOUT.
• Added predefined barrier signals: OsvvmTestInit, OsvvmResetDone, OsvvmTestDone, TestDone, OsvvmVcInit.
• CreateClock updated to add Offset, ClkActive, and Enable.
• Added CreateJitterClock.
• Added Scoreboard instances for unsigned, signed, and integer_vector.

 
Tested using: GHDL, NVC, Aldec RivieraPRO, Aldec ActiveHDL, Siemens Questa, Siemens Visualizer, Synopsys VCS, Cadence Xcelium, and Xilinx XSIM.

For full details see https://osvvm.org/downloads. Note there are some breaking changes and the “full details” provide information how to maintain backward compatibility.

Upcoming OSVVM Training Classes

We have a number of OSVVM class sessions coming up, including an in person opportunity in Bracknell, UK (sign up soon as class is filling). In addition, we have numerous on-line, instructor led classes. These classes accelerate your learning pace of OSVVM.   

 
Class details are at Advanced VHDL Testbenches and Verification – OSVVM™ Boot Camp.

SynthWorks’ on-line classes are instructor led, “half day” class sessions. For more details see
On-line class details.