Why OSVVM? › Forums › VHDL › How to compare compare std_logic and integer
This topic has 2 voices, contains 1 reply, and was last updated by Jim Lewis 1623 days ago.
A supposing easy question.
How to easily compare std_logic to integer of 0 and 1 without using “complex” “if then else” kind statement?
I was trying to find use assert to compare the std_logic and the input vector in integer.
CoveragePkg contains a to_integer function for both std_logic and boolean. So your assertion is no more than:
signal sig_std_logic : std_logic ;
signal sig_integer : integer ;
. . .
if to_integer(sig_std_logic) = sig_integer then
OTOH, if you are trying to compare a std_logic_vector, use the to_integer function from package, ieee.numeric_std_unsigned.
The following shows a way to randomize a value between 0 and 1 in std_logic:
TestProc : process
variable RV : RandomPType ;
variable B_sl : std_logic ;
(0 => B_sl) := RV.RandSlv(0, 1, 1) ;
You must be logged in to reply to this topic.
Please create an account to get started.
Proudly powered by WordPress and BuddyPress.