How to compare compare std_logic and integer

Why OSVVM™? Forums VHDL How to compare compare std_logic and integer

This topic contains 1 reply, has 2 voices, and was last updated by Avatar of Jim Lewis Jim Lewis 6 years, 9 months ago.

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  • #414
    Avatar of Steve Chan
    Steve Chan
    Member

    Hi expert

    A supposing easy question.

    How to easily compare std_logic to integer of 0 and 1 without using “complex” “if then else” kind statement?

    I was trying to find use assert to compare the std_logic and the input vector in integer.

    Thanks
      

    #415
    Avatar of Jim Lewis
    Jim Lewis
    Member

    Hi Steve,

    CoveragePkg contains a to_integer function for both std_logic and boolean.  So your assertion is no more than:

      signal sig_std_logic : std_logic ;
      signal sig_integer : integer ;
      . . .
      if to_integer(sig_std_logic) = sig_integer then
    

    OTOH, if you are trying to compare a std_logic_vector, use the to_integer function from  package, ieee.numeric_std_unsigned.

    The following shows a way to randomize a value between 0 and 1 in std_logic:

    TestProc : process

      variable RV : RandomPType ;
      variable B_sl : std_logic ;
    begin
      (0 => B_sl) := RV.RandSlv(0, 1, 1) ;
    

    Best, 

    Jim

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