OSVVM: VHDL’s #1 Verification Methodology

 
The 2024 Wilson Verification survey shows that OSVVM is being used by 35% of all FPGA designers world-wide, which makes OSVVM VHDL’s #1 Verification Methodology. Year after year we have made steady gains on UVM (SystemVerilog) in FPGA Verification. In Europe for FPGA, the 2022 survey showed that OSVVM is used more than UVM (38% to 20%).

Here are a few reasons why you should be using OSVVM:

A structured transaction-based framework

• Suitable for all verification tasks – from Unit/RTL to full chip/system level tests.
• Similar block diagram to SystemVerilog + UVM, except It plugs together just like RTL
• Facilitates re-use of VC and test cases through all levels of testing (RTL to Full Chip)

 
Model Independent Transaction (MIT) Library

• Defines Transaction API – procedures called by test case to build up sequences of interface operations – such as send, get, write, read
• Defines Transaction Interface – connects Verification Component to Test Sequencer.
• Used by all OSVVM defined VC

 
Verification component (VC) development

• Uses MIT library = building block level re-use.
• Makes development of a VC as simple as writing a procedure.
• No OO or fork and join – uses natural concurrency of a VHDL entity/architecture
• Any VHDL engineer can do this

 
Test cases

• Simplified since all VC of a similar type implement a subset of the MIT transaction calls (send, get, …)
• Directed tests or complex, randomized tests can be written by any VHDL engineer
• Readable and reviewable by the whole team including software and system engineers.

 
Unmatched Test Reports

• Build Summary – HTML (for humans) + JUnit XML (for CI tools)
• Test Cases – HTML
• Logs – HTML + plain text
• Requirements Tracking – HTML + CSV
• Helps Find and Debug issues faster

 
Powerful verification utilities that make VHDL a full verification language, including

• Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting (alerts), and message filtering (logs).
• Capabilities are simple to use, concise, and work like built-in language features.

 
Requirements Tracking

• Tracked using both OSVVM’s affirmations and functional coverage
• Tracks a count of each requirement and not just a boolean type check.

 
Scripting API

• Same script runs all simulators – including GHDL, NVC, Aldec Riviera-PRO and ActiveHDL, Siemens Questa and ModelSim, Synopsys VCS, and Cadence Xcelium.
• Is an API on top of Tcl
• Most scripts are just slightly more than a list of files
• Can run Tcl when you need it – usually no Tcl is required

 
Free, Open Source Verification Components include

• AXI Full and Lite, AxiStream, Wishbone, UART, xMII, SPI, DpRam, VideoBus.

 
Co-simulation

• Supports running software (C++) in a hardware simulation environment.
• Write test cases in C++
• Run C++ models such as instruct set simulators

 
Architected by a long-time IEEE VHDL working group contributor

• So expect better VHDL implementations.

 
It is Free, Open Source under APACHE 2.0

• Upgrades an ordinary VHDL license to a full featured verification capabilities
• On GitHub and IEEE Open Source.
• We accept issues and pull requests on GitHub.
• Join us.

 
Get similar verification capabilities to SystemVerilog + UVM without needing OO.
 
While OSVVM work is not sponsored by ESA (because we are in the US), at SEFUW 2025 (ESA’s Space FPGA Users Workshop) an ESA representative said that they do not mandate which methodology to use, but instead suggest that you use one of the major ones, such as OSVVM, UVVM, SystemVerilog + UVM, or Cocotb.
 

Check out my presentation from CERN’s FDF25 (FPGA Developers Forum) https://lecturemedia.cern.ch/2025/1467417c10/
 

The Wilson Verification Survey is sponsored by Siemens. The provided chart is derived from the one provided at https://resources.sw.siemens.com/en-US/white-paper-2024-wilson-research-group-fpga-functional-verification-trend-report/
 

Upcoming OSVVM Training Classes
We have a number of OSVVM class sessions coming up, including an in person opportunity in Bracknell, UK. In addition, we have numerous on-line, instructor led classes. These classes accelerate your learning pace of OSVVM.   
 

 
Class details are at Advanced VHDL Testbenches and Verification – OSVVM™ Boot Camp.

SynthWorks’ on-line classes are instructor led, “half day” class sessions. For more details see
On-line class details.