Named association of arrays to out ports illegal?

Why OSVVM?ForumsVHDLNamed association of arrays to out ports illegal?


This topic has 3 voices, contains 3 replies, and was last updated by Avatar of Andy Jones Andy Jones 274 days ago.

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May 3, 2016 at 08:10 #1162
Avatar of Torsten M.
Torsten M.

I had a nasty problem with a design, which could be localized after days of debugging. The cause of the problem seems to be using named association of std_logic signals to an out port of type std_logic_vector. The code looks like this:

port map (

  Valid_o => (0 => valid0, 1 => valid1),



A Synplify Pro version of 2014 synthesizes this code as intended. valid0 is assigned to Data_o(0), valid1 to Data_o(1).

A later version seems to understand the code in an other way, as it seems that it simply concatinates the two signals before association to the out port. In this case, the order of the signals is reversed, because the Data_o port is defined with descendent indexes.  valid0 is assigned to Data_o(1), valid1 to Data_o(0).

This results in a buggy design when testing it in FPGA device. In Modelsim DE 10.5, the construct is an error. The compiler says, “Formal Data_o of mode OUT cannot be associated with an expression”

But, which of the 3 behaviours is the correct one? I don’t have the LRM, but I can’t find any hint in the “Designers Guide to VHDL” that named association is forbidden when used with ports of mode out. This construct was in our code for years now without any problems. The problem arised when porting the design on a new version of the Microsemi Libero tool, which uses Synplify Pro as synthesis engine. We use VHDL-08.

May 3, 2016 at 09:54 #1163
Avatar of Jim Lewis
Jim Lewis

Hi Torsten
First a solution.  When port mapping, you can instead, index the formal:

port map (
  Valid_o(0) => valid0,
  Valid_o(1) => valid1,

AFAIK, aggregates on the LHS of an association were not legal until VHDL-2008.

There are some interesting things that happen with an aggregate that someone would have to research to understand what is going on here.

For example, with simple assignment assignment, the direction of the target is used when doing the following:

Valid_array <= (0 => valid0, 1 => valid1, ...) ;

However, once you put it in an expression, the direction becomes (0 to N-1):

Valid_array <= enable and (0 => valid0, 1 => valid1, ...) ;

There are a couple on stack overflow who would probably be willing to take the time to research this. I would recommend asking it there.


May 4, 2016 at 07:44 #1164
Avatar of Torsten M.
Torsten M.

Thanks Jim for your answer. Your solution is also the way I choose to get it running. Aggregates as a whole seem to be pretty complex. I will try to ask on stack overflow, if someone has an idea.

BTW, see you next week at your course :)

June 29, 2016 at 09:25 #1174
Avatar of Andy Jones
Andy Jones

Jim’s suggestion is good, but there are limitations:

You can’t use multiple index ranges, or an index range and individual index, in separate associations of parts of the same formal.

All formals that are elements of the same port must appear in consecutive associations (but the associations of a single aggregate port need not appear in any specific order). 

For example, you can’t do this:

input(0) => in_a,

output(0) => out_a,

input(1) => in_b,

output(1) => out_b,

The restrictions were probably intended to make it easier on the compiler to confirm that all elements of an aggregate formal are mapped, and none are repeated. 

Note that elemental formal associations also work with formals of a record type.


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