This topic has 3 voices, contains 4 replies, and was last updated by Avatar of Steve Chan Steve Chan 1420 days ago.

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February 1, 2013 at 09:23 #521
Avatar of Steve Chan
Steve Chan

*Hi all

I am planning to start embedding the more advance assertion contruct in my HDL/TestBench design.
My company is generally a VHDL house, but I can foresee use of SV in the future.
A mixed language environment is very likely to happen (as a matter it already exist)

I have read either PSL or SVA can work in both SV and VHDL.
So which assertion language should I pick in a mixed language enviornment.
What is the pro and con about the choice?

Steve Chan

February 1, 2013 at 09:51 #522
Avatar of Jim Lewis
Jim Lewis

Formally PSL is part of VHDL-2008.  Currently VHDL does not provide any access to the coverage/assertion information that PSL is tracking.  Hence, currently PSL and SVA provide similar capability.  

In the next revision of VHDL, we have proposals that address this oversight and give the testbench access to the coverage/assertion information in PSL.  At that point, PSL will have a significant advantage over SVA in the VHDL environment because the testbench can then adjust its test generation parameters to steer a test toward things that need to be generated.  

WRT to SV, I think OSVVM compares favorably.  OSVVM’s coverage capability is already a superset of SV.  SV has a constraint solver and OSVVM does not, however, I think this will be replaced by an intelligent testbenches.  See blog post, “Why no constraint solver?”

I am available for consulting and training if you need help getting the full power of OSVVM.  I also have additional packages that I currently release only to training and consulting clients.   You can reach me at

February 1, 2013 at 11:37 #523
Avatar of Steve Chan
Steve Chan

*Hi Jim

Thanks for your reply.

I have read Accellera no longer fund future VHDL development beyond 2008 (am I correct?).
It seems this may post challenge for the promotion of the new VHDL version 
How will that affect the future of the VHDL from your view?


May 10, 2013 at 05:21 #609
Avatar of Srinivasan Venkataramanan
Srinivasan Venkataramanan

My views on PSL vs. SVA for VHDL users:

1. PSL is more intuitive choice here as it has VHDL flavor (now that’s part of VHDL 2008). Hence both RTL and Verif team can add 9and debug) assertions. This is very important from a methodology standpoint of adopting ABV.

2. PSL historically has better support in Formal tools than SVA

3. PSL has some nice inheritance features that SVA (not SV-TB/class stuff) doesn’t have

4. PSL’s so called FL (Foundation Layer/language) sub-set is lot more efficient and intuitive to write succinct temporals than SEREs/sequences as in SVA (2005). Note: SVA-09 did add it and calls it LTL, but very few tools support it even today. So if you want to be productive PSL is THE way to go. See: for a small example on this.

5. PSL also has SV flavor, so learn one language, both VHDL & SV users can use it.

6. PSL works with E/Specman nicely with built-in action blocks (similar to Jim’s proposals), so this makes it even more compelling.

7.  Last but not the least – it is not all that difficult to migrate from PSL to SVA (or vice versa) if one needs in the future, so get productive with PSL today and if you ever have to migrate to SVA – it is not that hard.

Good Luck


May 10, 2013 at 08:04 #610
Avatar of Steve Chan
Steve Chan


Thanks for the clear explaination and the great insight.
This is very helpful.

Steve Chan

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