Using types defined in generic package for entity ports

Why OSVVM?ForumsVHDLUsing types defined in generic package for entity ports


This topic has 3 voices, contains 3 replies, and was last updated by Avatar of Andy Jones Andy Jones 273 days ago.

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June 26, 2016 at 16:03 #1169
Avatar of Torsten M.
Torsten M.

I have an interesting use case for a generic package, which I cannot get running. I have a generic package which defines 3 records with std_logic_vectors inside. Their lengths can be parametrized using a generic list in the package. It looks like this:

package test_p is

generic (ADDR_WIDTH : positive);

record t_test is

  data : std_logic_vector(ADDR_WIDTH-1 down 0);

end record t_test;

end package test_p;

How do I have to instantiate the generic package and where exactly? I didn’t have found any way, that Modelsim accepts. I want to set the generics depending on generics I give to an entity instance. So, the package instantiation have to be between generic & port definition of the entity definition. Is this possible? When not, what would be a work around which I could use?

  • This reply was modified 276 days ago by Avatar of Torsten M. Torsten M..
  • This reply was modified 276 days ago by Avatar of Torsten M. Torsten M..
June 27, 2016 at 07:31 #1172
Avatar of Torsten M.
Torsten M.

One possible work around I found at stack overflow is to use generic types in the entity ports list and to instantiate the generic package with the types included before instantiation of the entity in the architecture:

Have to try that with Modelsim later :)

June 27, 2016 at 08:07 #1173
Avatar of Jim Lewis
Jim Lewis

Hi Torsten,

I would have to know more about what you are trying to do to give you a good answer.  Here are a couple of ideas that may help.

1)  With VHDL-2008, composites (records and arrays) are permitted to have elements that are unconstrained.   With this capability, you constrain the array when you create a signal or variable.  Hence, you would not need to put a generic on the package.   For what I see, I would try this path first.   

Note, I have not used this in the OSVVM project as I am trying to minimize the amount of VHDL-2008 that I am using so I can get OSVVM working on more tools. 

2) With VHDL-2008, you can instantiate a package within an architecture and make it visible to the corresponding architecture.   If you must pass an entity generic to a package, this will help you accomplish it. The package instance looks like a normal package instance, other than it is in the architecture declarative area.  The use clause references the package as being local.  IE:  no library name because it is only visible locally (here  or to anything you pass the generic package to).

    use <PkgName>.all ;

This was what Martin was suggesting in his answer on stack overflow. 

If using a record with unconstrained elements (solution 1) works for you, it seems like it could be the simplest and most general approach.  

To use either of these, I would make sure you are using the most current release of your simulator. 

Best Regards,


June 30, 2016 at 10:09 #1175
Avatar of Andy Jones
Andy Jones

For option 2 to be meaningful, the entity needs to have visibility of the type (for its port declaration), in addition to the architecture. 

Also, somewhere outside the entity, will other signals or entities’ ports need this same type definition? IINM, if two instances of a generic package define a type, those two types are not the same type, and are not compatible, even if the same generic actuals were used on both package instances.


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