Generate Statement Breaks UART RX VC

Hello All,

I have a DUT which takes in serial data, deframes it, and demux’s it out to a 21 peripheral UART’s for transmission.

I have written an OSVVM testbench for this, as an exercise in familiarizing myself with OSVVM, and I have ran into one issue. Everything else works amazingly.

In my test harness, instead of declaring 21 instances of a UART_RX VC to receive data from my DUT, I wrapped it up into a generate statement as follows.

UART_VC_gen : for i in 0 to 20 generate
UART_RXD : UartRx
generic map
(
DEFAULT_BAUD => UART_BAUD_PERIOD_115200
)
port map
(
TransRec => Uart_rec(i),
SerialDataIn => serial_data_tx(i)
);
end generate UART_VC_gen;

I used array types of the appropriate records and serial data lines.

Everything worked well until I implemented scoreboarding to check my data, at which point it became apparent that the individual UARTs were somehow getting mixed up data. I verified that the UART serial data coming out of the DUT was correct, and so I concluded that the issue was with the VC.

My first step in debugging this issue was to unroll the generate statement and declare each VC individually, still using the record array, just indexing manually. lo and behold, this fixed the issue. The only difference that I can see is that the scoreboard_report.yml indicates that I now have 21 receive FIFO’s as well as 21 Scoreboards, whereas before I only had 1 receive FIFO and 21 Scoreboards.

This explains how the UART’s were getting access to each others data in the VC, and leads me to believe that somehow I am not generating the correct number of FIFO’s with my generate statement. As I mentioned, the issue is now fixed, but I would like to know if this is just a bug, or a misuse of OSVVM on my part. I much prefer the concise generate statement to individual VC declarations.

I apologize for the long winded question, but if you have any thoughts on this, I’d love to hear them.

Regards,
Michael