Introduction When writing a C or C++ program the entry point for execution is a main function which has a prototype definition as shown below: int main (int argc, char *argv[]); The parameters are used to pass in command line inputs from the user, with the first argument indicating how many arguments have been specified, including the name of the executable, and a pointer to an array of pointers t... »
Introduction In the previous OSVVM co-simulation article, I wrote about debugging co-simulation programs with GDB and how to add an IDE on top of this to give full dual debug capability with a software IDE, such as Eclipse, working alongside a GUI based logic simulator, such as Riviera-PRO or QuestaSim. This was about debugging the program that’s running on an OSVVM co-simulation node. One of the ... »
Introduction Co-simulation features were added to OSVVM at release 2023.01. This allows C or C++ code to be compiled for the machine hosting a logic simulator to be run as part of a logic simulation and interact with that simulation via a provide API, and I have written an introductory blog on osvvm.org in the past and there is, of course, a manual. With the introduction of software into a logic s... »
Introduction With the 2026.01 release of OSVVM a new verification component (or VC) was added to support the PCI Express (PCIe) bus protocol. OSVVM already has a comprehensive suite of VCs for both memory mapped address bus protocols, such as AXI, and streaming protocols, such as Ethernet. The PCIe VC extends OSVVM’s supported protocols as part of its ongoing development. However, there is somethi... »
The OSVVM 2026.01 release adds one big feature, PCIe CoSim Verification Component, and numerous smaller updates. PCIe CoSim Verification Component OSVVM now has a co-simulation based PCIe Verification Component thanks to Simon Southwell’s hard work. This reverses the typical co-simulation relationship where software communicates through the MIT interface to an OSVVM VHDL VC. Instead, ... »
Introduction The OSVVM Co-simulation features allow user supplied C or C++ code to drive model independent transaction (MIT) signals in a VHDL logic simulation via a supplied API, as I’ve discussed in a previous blog. When combined with one of the supplied Verification Components (VCs) or with a custom VC, the user software can generate protocol specific signalling to drive a design under te... »