Generic testControlProc – can this be a pattern?

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  • June 6, 2024 at 07:13 #2476
    Ajeetha Kumari
    Member

    Hi there,
    Coming from SV/UVM and the concept of design patterns applied to testbenches, am looking for common patterns in a typical OSVVM TB. Things such as:

    1. ClockGen
    2. ResetGen
    3. EndOfTestReport

    I believe the above 3 are straightforward (need to add #3 to my generator yet). What about some of the initialization code that I see in TbUart example:


    ------------------------------------------------------------
    -- ControlProc
    -- Set up AlertLog and wait for end of test
    ------------------------------------------------------------
    ControlProc : process
    begin
    -- Initialization of test
    SetTestName("TbUart_UartX16_1") ;
    SetLogEnable(PASSED, TRUE) ; -- Enable PASSED logs
    UartScoreboard <= NewID("UART_SB", NUM_UARTS) ;

    -- Wait for testbench initialization
    wait for 0 ns ; wait for 0 ns ;
    TranscriptOpen(OSVVM_RESULTS_DIR & "TbUart_UartX16_1.txt") ;
    SetTranscriptMirror(TRUE) ;

    -- Wait for Design Reset
    wait until nReset = '1' ;
    ClearAlerts ;

    -- Wait for test to finish
    WaitForBarrier(TestDone, 100 ms) ;
    AlertIf(now >= 100 ms, "Test finished due to timeout") ;
    AlertIf(GetAffirmCount < 1, "Test is not Self-Checking");

    TranscriptClose ;

    -- Create yaml reports for UART scoreboard
    osvvm_uart.ScoreboardPkg_Uart.WriteScoreboardYaml(FileName => GetTestName & "_sb_Uart.yml") ;
    EndOfTestReports ;
    std.env.stop ;
    wait ;
    end process ControlProc ;

    Can this be generalized and made to an entity of its own, with some inputs, and each TB/test can instantiate and pass custom args? Do you believe this is a common pattern in OSVVM TBs?

    Thanks
    Ajeetha

    June 7, 2024 at 03:09 #2483
    Jim Lewis
    Member

    Some of what is in the ControlProc is pretty standard. Some of it is not.
    The main items above that are custom are:

    UartScoreboard <= NewID("UART_SB", NUM_UARTS) ;
. . . 
osvvm_uart.ScoreboardPkg_Uart.WriteScoreboardYaml(FileName => GetTestName & "_sb_Uart.yml") ;

    Long term, we should be able to do the UartScoreboard as a constant:
    constant UartScoreboard : work.ScoreboardPkg_Uart.ScoreboardIDType := NewID("UART_SB", NUM_UARTS) ;

    Actually we can do right now as it works in the simulators. However, there is a sentence in the LRM that says you are not allowed to call the method of a protected type in a declaration region – NewID at a minimum does that indirectly.

    So far I have not been willing to step into the void of what works but is not officially supported by the language – however this one is special as it is an approved change and I have already done the edit to the LRM for the next version of VHDL.

    June 7, 2024 at 03:11 #2484
    Jim Lewis
    Member

    Depending on what becomes the pattern, it could be a concurrent procedure call (if it encapsulates the entire process), a sequential procedure call (if it only encapsulates most of the process), or as you suggested an entity (but may be more than we need).

    Also note that OSVVM’s TbUtilPkg has a CreateClock and a CreateReset

    June 7, 2024 at 09:21 #2485
    Ajeetha Kumari
    Member

    Thanks, aligns with my thoughts. Yes the generator already creates/uses clock/reset procedures.

    Regards
    Ajeetha

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