Reply To: The #if in VHDL

Doesn’t that feature only work with these things:

`if (TOOL_VENDOR = “Aldec”) and (TOOL_NAME = “Riviera-PRO”) then
constant VHDL_2019_STATUS : string := “With Aldec VHDL-2019 is here” ;

How will it work with things besides TOOL_VENDOR and TOOL_NAME? I do not understand why this feature has not been in VHDL from the start.

I mean using #if we can add ports, strip ports, include or exclude things as basic as a + or – sign or semicolon. Without #if, it would be impossible to generate all the different versions of design from that same source code. It is truly mind blowing what this feature can actually make possible.