VHDL port map between std_logic_vector(0 downto 0) and std_logic

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  • July 25, 2024 at 22:52 #2544
    Hassan
    Member

    When using generics to control data width of ports we could end up with std_logic_vector(0 downto 0) due to the data width being 1. When connecting this to an std_logic signal there is always an error of mismatch since there is std_logic_vector(0 downto 0) on on side and std_logic on the other side.

    The way to deal with this issue is to do this where we explictly specify the index 0 of the 1 bit std_logic_vector;

    i_delay_last : entity common_lib.delay_chain
    generic map (
    DATA_WIDTH => 1,
    DELAY_CLKS => STAGES
    )
    port map (
    i_clk => i_clk,
    i_cke => cke,
    i_d(0) => s_axis_tlast,
    o_q(0) => m_axis_tlast
    );

    My question is, what is the reason that VHDL does not automatically work out that a 1 bit std_logic_vector is being connected to std_logic and work straight away?

    September 5, 2024 at 09:34 #2566
    Eilert Backhus
    Member

    Hello Hassan.
    It’s one of the fundamental concepts of VHDL: Strong Typing.

    A vector is a different type than its base type.

    You have mentioned a specific corner case: (0 downto 0)
    As you mentioned this was the result of some generics, which means at some other time this vector could also result in e.g. (6 downto 0).

    Now consider that your code actually contains a line like
    my_SL <= some_SLV;

    For every other case than your example this obviously must create an error, since N bits won’t fit into one bit.

    If there would be an exception made for your example case and you would test your design with it everything would look fine, but as soon as you (or someone else) tries any other case you would get errors.
    Great confusion and pondering what’s wrong, hours of work wasted.

    And, speaking more basically, if your design contains such an assignment it is doomed to fail since it can not handle Vectors, which will appear as soon as the Generic changes.

    Also, if you are really just looking for a single Bit of that vector you have to give the index number in the assignment anyway. It might be constant or also depending on that same generic. Then, considering there might be a flaw in the index calculation, the compiler might be able to find that error during compilation.

    So Strong Typing helps you to avoid and identify design errors at an early stage.

    A momentary convenience can come with a cost later on.

    Have a nice synthesis
    Eilert

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