Reply To: VHDL port map between std_logic_vector(0 downto 0) and std_logic

Hello Hassan.
It’s one of the fundamental concepts of VHDL: Strong Typing.

A vector is a different type than its base type.

You have mentioned a specific corner case: (0 downto 0)
As you mentioned this was the result of some generics, which means at some other time this vector could also result in e.g. (6 downto 0).

Now consider that your code actually contains a line like
my_SL <= some_SLV;

For every other case than your example this obviously must create an error, since N bits won’t fit into one bit.

If there would be an exception made for your example case and you would test your design with it everything would look fine, but as soon as you (or someone else) tries any other case you would get errors.
Great confusion and pondering what’s wrong, hours of work wasted.

And, speaking more basically, if your design contains such an assignment it is doomed to fail since it can not handle Vectors, which will appear as soon as the Generic changes.

Also, if you are really just looking for a single Bit of that vector you have to give the index number in the assignment anyway. It might be constant or also depending on that same generic. Then, considering there might be a flaw in the index calculation, the compiler might be able to find that error during compilation.

So Strong Typing helps you to avoid and identify design errors at an early stage.

A momentary convenience can come with a cost later on.

Have a nice synthesis
Eilert