Vivado : Error with AXI Data width

This topic has 2 replies, 2 voices, and was last updated 1 day ago by Remy.

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October 27, 2025 at 16:24 #2794

Remy
Member

Hello,
I am using OSVVM 2025 with Vivado 2025.1.1.
I started from the AXI example.
When I change the values of AXI_ADDR_WIDTH to 16 and AXI_DATA_WIDTH to 256, the signals sWData, sWValid, and sWReady become undefined.
Is this bug dependent on Vivado or AXI drivers?

October 27, 2025 at 16:54 #2795

Jim Lewis
Member

Hi Remy,
Can you share exactly what you updated? Is it a particular OSVVM testbench or one of your own?

The test cases that do bursts as words will not work as they likely have dependencies on a specific size interface. The test cases that do bursts as bytes are expected to work though.

Best Regards,
Jim

October 28, 2025 at 07:50 #2797
Remy
Member
Hi Jim,
I updated the AXI FULL OSVVM testbench available here.
```
architecture TestHarness of TbAxi4 is
  constant AXI_ADDR_WIDTH : integer := 16 ;
  constant AXI_DATA_WIDTH : integer := 256 ;
  constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH/8 ;
```
I modified the width of AXI DATA and AXI ADDR, and adapted the test cases to include the new data and address sizes.
```
  ManagerProc : process
    variable send_Data : std_logic_vector(AXI_DATA_WIDTH-1 downto 0) ;
    variable send_Addr : std_logic_vector(AXI_ADDR_WIDTH-1 downto 0) ;
    variable y : integer;

  begin
    wait until nReset = '1' ;  
    WaitForClock(ManagerRec, 2) ; 
    for y in 0 to 10 loop
     send_Addr := ( '1', others => '0') ;
     send_Data := ( '0', '1' ,others => '0');
     Write(ManagerRec, send_Addr, send_Data) ;
     WaitForClock(ManagerRec, 10) ; 

    end loop;

    WaitForClock(ManagerRec, 2) ;
    WaitForBarrier(TestDone) ;
    wait ;
  end process ManagerProc ;
```
Regards,
Remy
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