coverage in rtl

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  • January 8, 2015 at 02:56 #921
    raphael H
    Member

    Hi,

    So far I just looked at the webinar from Aldec.

    I was wondering if the coverage package is supposed to be used only in test-benches (All the examples is the user guide are in entity called tb….) or if the methodology allows adding coverage code in an RTL design to check coverage without affecting the synthesis of that design.

    thanks,

    raph

    March 8, 2015 at 15:55 #937
    Jim Lewis
    Member

    Hi Raph,

    Currently there are no metacomments (– Synthsis off) to allow usage during synthesis.   Not sure if it would work or not since it does require the methods of the protected type to be visible.  

    I have instead used VHDL-2008 external names to reach down into the design from the testbench level. 

    Best Regards,

    Jim

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