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#1 – If stopping the simulation with assertion or std.env.stop, it was not a “real” stop.
Hitting the “run all” button in the simulator would let the test bench continue to run endlessly.
Personally I don’t feel like this behavior.

Stopping the clock is the true end. When the simulator stops, there is nothing more to simulate.
Hitting the “run…[Read more]

Hi Jim,

Thanks for the quick response.

#2 – Some learning experience here.
I started the journey by studying the example test bench TbAxi4_BasicBurst.
The example went broken as soon as I changed AXI_DATA_WIDTH to a wider one in TbAxi4.
Looking back, it was probably the test cases.
But at that time I did not realized that the test was doing…[Read more]

Hi Chengshan,

>1. Could the test bench be stopped gracefully by stopping all clocks?
Do you have a method to gracefully stop clocks? Everything I have seen
has overhead incurred at least once per clock cycle (or some multiple of
the clock cycle).

OTOH, I really like std.env.stop. It only incurs overhead when
it is actually stopping the…[Read more]

Hi Chengshan,

3. Correct. The 2020.08 Axi4Responder_Transactor.vhd is intended to be a register access model and does not support bursting. As you noted, Axi4Memory.vhd, implements memory models and does support bursting. This is noted in the README.md at: https://github.com/osvvm/AXI4.

Do you need a transactor that supports bursting? It…[Read more]

Hi Chengshan,

2. The test sequencer interface to AXI verification component burst FIFO is 8 bits. The AXI verification component assembling this into the size of the data bus. So you will always push bytes into the FIFO – even if you make the data bus bigger or smaller. It was tested with a 32 bit AXI data bus, however, it is intended to…[Read more]

Hi Chengshan,

4. Typo! You are correct, AxRegion should be 4 bits. I will fix that
in the next release. Anything else like that is an issue?

What do you mean you had to change the width to make it compile? Is this to
connect it to your design? It compiles and runs fine with the OSVVM models
which all use the same incorrectly sized…[Read more]

Hi Chengshan,
First, thanks for the feedback.

Are you using this with a particular design?

You have four questions, so I will give 4 separate answers.

Best Regards,
Jim