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Jim Lewis replied to the topic Weird QuestaSim Base Error in the forum OSVVM 1 day, 14 hours ago
Hi Nigel,
In the OSVVM 2024.09 and 2025.02 releases, the 2019 compile switch was turned on if the Questa release is greater than 2024.2. With the OSVVM 2025.04a release and beyond the 2019 switch it is turned back off again. So I recommend getting the newest release of OSVVM (2025.06a) and this problem is resolved.In Questa, your issue is…[Read more]
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Jim Lewis replied to the topic Weird QuestaSim Base Error in the forum OSVVM 1 day, 14 hours ago
Hi Nigel,
In the OSVVM 2024.09 and 2025.02 releases, the 2019 compile switch was turned on if the Questa release is greater than 2024.2. With the OSVVM 2025.04a release and beyond the 2019 switch it is turned back off again. So I recommend getting the newest release of OSVVM (2025.06a) and this problem is resolved.In Questa, your issue is…[Read more]
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Alain became a registered member 1 day, 16 hours ago
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Pablo became a registered member 1 day, 20 hours ago
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Nigel started the topic Weird QuestaSim Base Error in the forum OSVVM 2 days ago
Got a bit of a strange one here. I finally had to bite the bullet and let go of ModelSim DE and upgrade to QuestaSim Base. Straight away I ran into a problem with my simulations that use OSVVM (my sims that don’t use OSVVM work fine). When running the sim, Questa reports the following error:
** Error:…[Read more]
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Mikael replied to the topic Safer Check if Simulation passed or Not in the forum OSVVM 3 days, 2 hours ago
The Report APIs should be there in Questa sim 2025.2.
The latest Questasim version is now 2025.3Remember that today, mixed language designs are very common. Some IPs are only available in Verilog.
So it is not just VHDL assertions that can be a source of errors.
There could be SVA assertions, both immediate and concurrent.IPs or library…[Read more]
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Jim Lewis replied to the topic Safer Check if Simulation passed or Not in the forum OSVVM 3 days, 17 hours ago
Hi Mikael,
This is a good point. In VHDL-2019, we put things in that will allow OSVVM to collect error information from VHDL and PSL assertions. Sounds like a great addition for the next release.Do you know which version of Questa started supporting the following subprograms from std.env:
For VHDL Asserts:
GetVhdlAssertCount,…[Read more] -
Mikael replied to the topic Safer Check if Simulation passed or Not in the forum OSVVM 4 days, 1 hour ago
By saving the UCDB file for each testcase (<testname>.ucdb , you can also check the teststatus afterwards:
>vcover attribute OsvvmTemp_Questa/TbAxi4_DemoMemoryReadWrite1.ucdb
The tcl procedure I use to check the test status,just contact me and I will send it. Seems like the code is blocked.
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Mikael started the topic Safer Check if Simulation passed or Not in the forum OSVVM 4 days, 1 hour ago
Today the outcome of the simulation is solely dependent on the OSVVM report server and if you have triggered an error or not.
But if you have for example an external library cell/ip that uses assertions, it can still look as the simulation passed while it indeed failed.I added “assert false” in a testcase to illustrate the problem. This is the…[Read more]
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MOhd became a registered member 4 days, 4 hours ago
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Mikael became a registered member 4 days, 9 hours ago
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Fatemeh became a registered member 4 days, 22 hours ago
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Remy became a registered member 4 days, 22 hours ago
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Bruno became a registered member 5 days, 3 hours ago
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Mikael became a registered member 1 week, 1 day ago
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Karl's profile was updated 1 week, 1 day ago
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Andy became a registered member 1 week, 2 days ago
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Hassan replied to the topic Parallel Simulations in OSVVM and VUnit Integration in the forum OSVVM 1 week, 5 days ago
Is there any update on this i.e can we now generate the reports of OSVVM from VUnit test framework based testbench?
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Adam became a registered member 2 weeks, 1 day ago
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Jerzy Gbur replied to the topic Vivado and OSVVM in the forum OSVVM 2 weeks, 4 days ago
Ok, I found it, need to use depricated module LanguageSupport2019Pkg_c.vhd – there is overloaded “to_string” function inside.
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