VHDL in general – Page 2 – Open Source VHDL Verification Methodology

Ian Gibbins December 21, 2012 VHDL in general 0

Let’s Meet At DAC…

Ian Gibbins May 16, 2012 Event, OS-VVM in general, VHDL in general 1

Semi-formal meeting of OS-VVM fans and VHDL users will be held at the 49th Digital Automation Conference (DAC 2012). The conference is located in San Francisco, California, USA this year. The entry to the exhibit hall at Moscone Center is free on Monday, June 4th – drop in if you happen to be in the area. We are meeting at the ALDEC booth (#2126) at 2pm. To help us estimate how many visitors... »

The (not so) Good Old Stuff

Ian Gibbins April 13, 2012 VHDL in general 1

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Posting VHDL code in blog or forum

Ian Gibbins April 10, 2012 Internet, VHDL in general 2

Posting plain text in the blog or forum should not be a problem to anybody who can type – no knowledge of programming languages is necessary. If, however, somebody wants to post a snippet of VHDL code, situation changes dramatically… First, the poster has to know what format is expected: plain text, rich text, HTML? Then the plain VHDL code must be converted to proper format (with exce... »