Reply To: OSVVM 2020.08 New user experience
4. Typo! You are correct, AxRegion should be 4 bits. I will fix that
in the next release. Anything else like that is an issue?
What do you mean you had to change the width to make it compile? Is this to
connect it to your design? It compiles and runs fine with the OSVVM models
which all use the same incorrectly sized AwRegion/ArRegion.
In general, as an example of how to handle a situation like this, take a
look at Axi4/testbench/TbAxi4.vhd. Any composite interface can be mapped
element by element – provided all the elements are mapped and that once you
start mapping an array element that you finish mapping all of it. In this
case, that means that if you did not (or could not modify the other code)
you could connect a 4 bit “dummy” signal to the unused bits of AwRegion/ArRegion.
Based on the example from TbAxi4.vhd, if you run into a problem like this
with other models (and you don’t have access to edit them), you can do the
Axi4Minion_1 : Axi4Responder port map ( -- Globals Clk => Clk, nReset => nReset, -- Testbench Transaction Interface TransRec => AxiMinionTransRec, -- AXI Master Functional Interface AxiBus.WriteAddress.Addr => AWAddr , AxiBus.WriteAddress.Prot => AWProt , AxiBus.WriteAddress.Valid => AWValid , AxiBus.WriteAddress.Ready => AWReady , AxiBus.WriteAddress.ID => AWID , AxiBus.WriteAddress.Len => AWLen , AxiBus.WriteAddress.Size => AWSize , AxiBus.WriteAddress.Burst => AWBurst , AxiBus.WriteAddress.Lock => AWLock , AxiBus.WriteAddress.Cache => AWCache , AxiBus.WriteAddress.QOS => AWQOS , AxiBus.WriteAddress.Region(7 downto 4) => ErrorAwRegion(3 downto 0), -- the erroneous piece AxiBus.WriteAddress.Region(3 downto 0) => AWRegion, -- the correct piece AxiBus.WriteAddress.User => AWUser ,
Thanks again for catching this. I have already edited my private
dev branch. Will push it to the github dev branch as soon as I