Reply To: OSVVM 2020.08 New user experience
2. The test sequencer interface to AXI verification component burst FIFO is 8 bits. The AXI verification component assembling this into the size of the data bus. So you will always push bytes into the FIFO – even if you make the data bus bigger or smaller. It was tested with a 32 bit AXI data bus, however, it is intended to work with any legal AXI width data bus.
It was not tested with a 64 bit interface. What width are you using?
Can you send me a test case – my email address jim at synthworks.com.