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#1718
Jim Lewis
Member

#2 Did you run the testbench examples before modifying them? The test TbAxi4_MemoryBurst (which runs when you do build ../OsvvmLibraries/AXI4/Axi4/testbench) does bursts. The first burst in the test is 3 32 bit words – IE 12 bytes and the address is word aligned.

What is 1 wider? Did you mean 64 bits? AXI data supports a power of 2 bytes in a transfer (ie: 1, 2, 4, 8, 16, …).
I am not sure what you mean by narrow transfers. At the end of TbAxi4_MemoryBurst, oddly small bursts are being tested. This is not meant to demonstrate how to do bursts – instead it is intended to verify that the model supports small bursts – as it is required to do.