Reply To: Generate Statement Breaks UART RX VC
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Unfortunately this impacts all OSVVM VC. So the same change is needed for the UartTx.
Are you using sources from OSVVM.org or GitHub? I have updated the GitHub dev branch. I will update the main branch tomorrow. If you are using sources from OSVVM.org, I will update them too, otherwise, they will be updated when 2022.05 is released.
With the addition of the MODEL_ID_NAME, the recommended practice will be:
UART_VC_gen : for i in 0 to 20 generate UART_RXD : UartRx generic map ( MODEL_ID_NAME => "UartRx_" & to_string(i), DEFAULT_BAUD => UART_BAUD_PERIOD_115200 ) port map ( TransRec => Uart_rec(i), SerialDataIn => serial_data_tx(i) ); end generate UART_VC_gen;
I did not actually test the above code, but I did test similar code that is in OsvvmLibraries/AXI4/Axi4/testbench_MultipleMemory/TbAxi4_MultipleMemory_Generate.vhd
Again this test case is on the dev branch of the Axi4 libraries.