Reply To: Custom VC for image-sensor interface

[fpgaphreak]

My question would be what the intention is in detail: Typically sensor interfaces are simulated and tested independently from the image content. Therefore I produced a test package capeable of driving various signal schemes and bahaviour into the lvds lines which can be simulated and also synthesized into an FPGA for real investigations of eye patterns.

The other issue is the image content like defective pixels, stuck-at pixel and the typical fixed pattern / non uniformity issues which require various runs of simulation which at the time can be done with compiled simulations only (HDL Coder) with the full image.

I wonder if there is a possible approach to simplify this by an intelligent frame work leaving out the fields without interest, or reveals already processed data respectively.
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