Hi fpgaphreak,
I have two main goals with this test bench:
– Check that pixel values generated on the sensor input appear in the appropriate form on the AXI-Stream output, and completion interrupts and status registers are set correctly
– Check that the interface logic is well-behaved in the case of errors on the LVDS inputs, i.e., no FSM deadlocks, well-formed output, and correct error interrupts and status registers
