Reply To: Verification with SystemVerilog or VHDL

[Oliver]

Hi Jim,
thanks for the link. Now that I finally got my tools working I will have a look at it soon. The OSVVM demo tests look good and run well (not when following the old user’s guide in the OSVVM Examples zip archive on this site though). Unfortunately the simulation of Xilinx PCIe-demo-design with Vivado will not run when the language is set to VHDL ([XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.). There are problems with generics. Only in Verilog it will run.

Best regards
Oliver