Reply To: Learning OSVVM with AXI4

[Jim Lewis]

Hi Adam,
WRT randomness in dispatching each channel, that is what I am currently working on. I added it to AxiStream in a Beta form in an earlier OSVVM release – it has changed some on the Dev branch. I will be adding it to Axi4 VC next. Each channel will be independent, so a write data should randomly happen prior to write address, as will random pauses. I can let you know when it is in the Dev branch if you like.

You can have write data happen before write address by using the asynchronous and single channel operations. If you want to do this in a determinist fashion, then you can do:

-- WriteDataAsync needs ByteAddr to determine the ByteEnables.  It is typically a value.  If left off, 0 is used.
WriteDataAsync(ManagerRec, ByteAddr, X"AA00") ;   
WaitForClock(ManagerRec, 2) ; 
WriteAddressAsync(ManagerRec, X"A0000") ; 

If you want to drive the Read and Write interfaces from separate processes, you can use two separate instances of the Axi4Manager VC as you suggested. Alternately, if you just want to do read and write operations simultaneously, you can use the asynchronously dispatched operations as shown below. The downside to this is that the ReadCheckData is blocking (there are plans to address this too, however, it is further out than randomization).

for i in 1 to 5 loop 
    WriteAsync(ManagerRec, "X10000"+i, X"1000"+i) ; 
end loop ; 
WaitForClock(ManagerRec, 2) ; -- Add enough wait for one write to complete
for i in 1 to 5 loop 
    ReadAddressAsync(ManagerRec, "X10000"+i) ; 
end loop ; 
for i in 1 to 5 loop 
    ReadCheckData(ManagerRec, X"1000"+i) ;  -- These block until data is available
end loop ;  

Cheers,
Jim