Reply To: Learning OSVVM with AXI4

[Joseph]

Hi Jim,

Thanks for the speedy reply. I can’t post the DO file, but I can try to post the what it is supposed to do. This test bench passes vector files which poke around registers. The vector files use a custom API that my team developed that go through a VHDL file to a VHDL test bench. It is based on OSVVM, but there’s the extra layer from our custom API. There are some Verilog and Systemverilog files involved in the project.

set variables to directories
set variables to default command line options

while loop parsing command line options from ModelSim command line and sets variables to them

a number of vlib, vmap, vcom, vlog, and vsim commands for various files and folders

I’m quite limited in what I can post. I hope it’s enough to get somewhere. It’s a pretty complicated DO file.

It sounds like I would have to translate that into a PRO file. Is there a way it could be called in a TCL file and that be called in a PRO file? Or is there a way to put the coverage controls into the DO file itself? Can OSVVM compile Verilog or Systemverilog files?

Thanks,
Joseph