Reply To: Scripting dual-language testbench (VHDL / Verilog)

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October 4, 2023 at 01:13 #2295
Jim Lewis
Member

Have you tried:

simulate DUT_test glbl -L unisim [generic C_EXAMPLE_PARAM 1]

What library is glbl in? If it were VHDL and glbl is in the unisim library, the glbl would be referenced as unisim.glbl.

If all of your simulations use glbl and unisim library, you can do:

SetExtendedSimulateOptions "-L unisim"
SetSecondSimulationTopLevel glbl
simulate DUT_test [generic C_EXAMPLE_PARAM 1]
simulate ...