Reply To: Scripting dual-language testbench (VHDL / Verilog)

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October 4, 2023 at 19:43 #2296
Brad Adam
Member

Hey,

glbl is a verilog file referenced by an IP from a third party vendor.

Is it possible to set a generic for a file that is analyzed before simulation? Looking at the script users guide I would think that SetExtendedAnalyzeOptions is meant to accomplish this but I could be using the command incorrectly. Is it possible to use SetExtendedAnalyzeOptions to set the value of a generic in a specific analyzed file?

In this case DUT_test would be a configuration of the main DUT_TB entity defined in a separate file, so I’m trying to set a generic set in DUT_TB which is analyzed before simulating DUT_test.

Thanks!