Reply To: Scripting dual-language testbench (VHDL / Verilog)

Why OSVVM™? Forums OSVVM Scripting dual-language testbench (VHDL / Verilog) Reply To: Scripting dual-language testbench (VHDL / Verilog)

Jim Lewis

In OsvvmLibraries/Ethernet/TestStandAlone/, I set the generics for the top level test by doing:

simulate Tb_xMii1 [generic MII_INTERFACE RGMII] [generic MII_BPS BPS_1G]

Here Tb_xMii1 is the name of the configuration for the testharness (named TbStandAlone).

So if you have not already, add top level generics to the testharness that are then mapped to lower level blocks. Looking at the example above may help some.

From the RiveraPRO command reference on asim/vsim,

Assigns values to VHDL generics, Verilog and SystemVerilog parameters, and SystemC generics that are not assigned values in VHDL generic maps or through the Verilog/SystemVerilog defparam statement. Has no effect on SystemVerilog parameterized classes.
The name part of the argument can include a relative or hierarchical path (without the dataset logical name, i.e. without string sim: at the beginning). For example:

So if you have mapped a lower level generic, it does not look like you can override it with this. So instead, have a top level generic that is not mapped, and connect it to the lower level examples – just like done in the Ethernet testharness.