Reply To: Scripting dual-language testbench (VHDL / Verilog)

[Brad Adam]

Okay, this is very helpful information and from this I believe the answer to what I am trying to do is probably no.

Looking at TestStandAlone.vhd assume there is a generate statement that decides if xMiiPhy gets created or not.

phy_gen : if C_PHY_GEN_TRUE = 1 generate

  xMiiPhy_1 : xMiiPhy 
    generic map (
      MII_INTERFACE  => MII_INTERFACE,
      MII_BPS        => MII_BPS, 
      DEFAULT_DELAY  => tpd
    ) 
    port map (
      -- xMii Transmitter Functional Interface
      GTx_Clk       => GTx_Clk      ,
      Tx_Clk        => Tx_Clk       ,
      TxD           => TxD          ,
      Tx_En         => Tx_En        ,
      Tx_Er         => Tx_Er        ,
      Tx_Ctl        => Tx_Ctl       ,
      
      -- xMii Receiver Interface
      Rx_Clk        => Rx_Clk       ,
      RxD           => RxD          ,
      Rx_Dv         => Rx_Dv        ,
      Rx_Er         => Rx_Er        ,
      Rx_Ctl        => Rx_Ctl       ,
      Crs           => Crs          ,
      Col           => Col          ,
      
      -- Testbench Transaction Interface
      PhyTxRec     => PhyTxRec    ,
      PhyRxRec     => PhyRxRec
    ) ;

end generate phy_gen;

In the above code passing something like MII_INTERFACE into the xMiiPhy using the simulate commands makes total sense, those generics will not be needed before simulation begins. However, C_PHY_GEN_TRUE is needed before simulation of a testcase occurs.

Does OSVVM assume that generics will not be used in this way? If this is not recommended for OSVVM I will restructure my testbenches going forward but I wanted to be sure I wasn’t missing something simple that would allow me to control a generate statement in the TB before running a dependent testcase.