Reply To: Scripting dual-language testbench (VHDL / Verilog)

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#2300
Jim Lewis
Member

Hi Adam,
If C_PHY_GEN_TRUE is a top level generic, OSVVM will allow you to specify it for either simulate or RunTest. As long as your simulator supports that, it should work just fine. Generate is resolved at elaboration time – which is the first step of simulation.

Have you tried something like this and it failed to work?

Jim