Reply To: Scripting dual-language testbench (VHDL / Verilog)
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Yes, this fails before the simulation phase is ever reached because I have two testbenches that are testing two versions of a DUT which has a different port list in each testbench but use the same TB file. These two testbenches have separate .pro files and test cases but they share the TB file. When analyzing that TB file, since the generic has not been set to control the generate statement yet the simulation fails as it sees signals from the other DUT which is meant NOT to be generated and throws “unknown identifier” errors.
I’m fairly certain that in the OSVVM Ethernet example, if for whatever reason two versions of ethernet were using TestStandAlone.vhd with generate statements to create one version of the DUT or the other, it would encounter the same issue.
“analyze TestStandAlone.vhd” would fail because the generic that controls which version of the DUT is created would not be set until the next line, “RunTest Tb_xMii1.vhd”.
Luckily its pretty easy to just split the TB file into two, one for each version of the DUT. I just thought I must be missing something because during initial testing I was using a constant variable to generate the correct DUT during analyze just fine but when I pulled that constant to the top level as a generic it broke the testbench.