Reply To: Why does VHDL require explicit conversion from signed/unsigned to logic vector?

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July 29, 2024 at 19:40 #2547
Jim Lewis
Member

Like types integer and real, the types signed, unsigned, and std_logic_vector are different types.

One really cool thing about different types is they support independent overloading, hence, the “+” operator for signed is unique and different from the “+” operator for unsigned. If they automatically converted this would not be possible.