Reply To: Why does VHDL require explicit conversion from signed/unsigned to logic vector?

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#2550
Hassan
Member

In the VHDL as it exists today, we must use numeric_std. No arithmetic is thus possible with std_logic_vector, we must use signed or unsigned.

I do not understand, what logic or arithmetic principle is broken when signed is converted to std_logic_vector implicitly or unsigned is converted to std_logic_vector implicitly.

I am merely talking about this type of scenario as an example:

entity cntr is
port (
i_clk : in std_logic;
..
o_q : out std_logic_vector(3 downto 0)
);
end entity;

architecture rtl of cntr is

signal value : unsigned(o_q’range);

begin

— This below line is invalid VHDL
o_q <= value;

end architecture;