Reply To: Waveforms not generated correctly (GHDL)

[Patrick]

Usually, you can trust the synthesis tools. If you really mistrust them, you should skip post-synthesis and post-placement simulation and go to post-routing simulation. Post-synthesis is just after synthesis without optimization, placement and routing. So you would miss critical parts in the transformation from VHDL to bitstream.

Please keep in mind, you need to drive your data differently in post-*** simulations, as almost all wires have delays on them. A simple behavioral simulation without delays can’t be easily used to drive and check a post-*** simulation. OSVVM verification IPs have lots of tpd parameters, so you can set propagation delays for every signal in relation to clock.

I never needed a post-*** simulation in designs. The tool bugs I had so far (the list is not short …) wouldn’t be discoverable with this kind of simulation.

Also, timing simulations (post-*** simulations are timing simulations) don’t discover timing problems. They check your design for a subset of value transitions, but you can’t find (compute) all input combinations (sequence of inputs) to trigger the internal worst case, which will potentially surface the critical path.