Reply To: About cyclic randomlike the randc of SystemVerilog

Why OSVVM™? Forums OSVVM About cyclic randomlike the randc of SystemVerilog Reply To: About cyclic randomlike the randc of SystemVerilog

Ian Gibbins


The quick answer is: you cannot do it in a quick and easy manner. You have to do some manual coding to get the required results. Let me explain quickly why:

  • implementation of randc is memory hungry: for k-bit number you want to randomize you need at least n=2k element array to store permutations,
  • algorithm for selecting sequences is time consuming and uses resources in very uneven manner.

Here is an outline of the algorithm:

  1. Create n-element array A (let’s say that it is indexed 0 to n-1)
  2. Fill array A with desired numbers ordered from minimal to maximal
  3. Create for loop with counter i and value range n-1 downto 1
  4. Within the loop you have to generate random number j from the range 0 to i and
  5. Swap A(i) with A(j) and go to the next loop iteration
  6. Initialize randc counter r to 0
  7. For each randc call return A(r) and increment r
  8. When r reaches n, jump to step 3.

As you see, flexible implementation of this algorithm requires smart decisions to balance memory usage and execution speed. We will investigate further, but for now I recommend creating fixed implementation suited to your particular needs.

One more thing, SV implementation of randc that meets  LRM requirements cannot be really random! I will post explanation in the blog section soon.

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