Reply To: Named association of arrays to out ports illegal?

[Jim Lewis]

Hi Torsten
First a solution.  When port mapping, you can instead, index the formal:

port map (
  Valid_o(0) => valid0,
  Valid_o(1) => valid1,
  ...
);

AFAIK, aggregates on the LHS of an association were not legal until VHDL-2008.

There are some interesting things that happen with an aggregate that someone would have to research to understand what is going on here.

For example, with simple assignment assignment, the direction of the target is used when doing the following:

Valid_array <= (0 => valid0, 1 => valid1, ...) ;

However, once you put it in an expression, the direction becomes (0 to N-1):

Valid_array <= enable and (0 => valid0, 1 => valid1, ...) ;

There are a couple on stack overflow who would probably be willing to take the time to research this. I would recommend asking it there.

Jim