Reply To: Named association of arrays to out ports illegal?
Jim’s suggestion is good, but there are limitations:
You can’t use multiple index ranges, or an index range and individual index, in separate associations of parts of the same formal.
All formals that are elements of the same port must appear in consecutive associations (but the associations of a single aggregate port need not appear in any specific order).
For example, you can’t do this:
input(0) => in_a,
output(0) => out_a,
input(1) => in_b,
output(1) => out_b,
The restrictions were probably intended to make it easier on the compiler to confirm that all elements of an aggregate formal are mapped, and none are repeated.
Note that elemental formal associations also work with formals of a record type.