Reply To: OSVVM TestBench needs Access to EXTERNAL FSM_STATE Enum Type

Why OSVVM™? Forums VHDL OSVVM TestBench needs Access to EXTERNAL FSM_STATE Enum Type Reply To: OSVVM TestBench needs Access to EXTERNAL FSM_STATE Enum Type

#1244
Dave Ansell
Member

Thanks for your reply.

So 

as I thought, there is NO other way of doing it Without MODs to DUT

&

This Rules out generated Code.

So VHDL Needs Fixing

The most Flexible Fix would be:-

ALIAS FSM_STATE_TYPE_HANDLE is \<\<TYPE DUT.FSM_STATE_Type : NULL\>\>;

But

ALIAS FSM_STATE_HANDLE is \<\signal DUT.FSM_STATE : INCOMPLETE_Type_Name\>\>;

Would be OK

I won’t hold my breath for the next Version of VHDL.

In the Meantime I’ll use a Duplicate Type Declaration because ModelSim accepts it even though IT SHOULDN’T.