Reply To: PSL or SVA?

[Jim Lewis]

Formally PSL is part of VHDL-2008.  Currently VHDL does not provide any access to the coverage/assertion information that PSL is tracking.  Hence, currently PSL and SVA provide similar capability.  

In the next revision of VHDL, we have proposals that address this oversight and give the testbench access to the coverage/assertion information in PSL.  At that point, PSL will have a significant advantage over SVA in the VHDL environment because the testbench can then adjust its test generation parameters to steer a test toward things that need to be generated.  

WRT to SV, I think OSVVM compares favorably.  OSVVM’s coverage capability is already a superset of SV.  SV has a constraint solver and OSVVM does not, however, I think this will be replaced by an intelligent testbenches.  See blog post, “Why no constraint solver?”  https://osvvm.wpengine.com/archives/458

I am available for consulting and training if you need help getting the full power of OSVVM.  I also have additional packages that I currently release only to training and consulting clients.   You can reach me at jim@synthworks.com