Reply To: PSL or SVA?
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My views on PSL vs. SVA for VHDL users:
1. PSL is more intuitive choice here as it has VHDL flavor (now that’s part of VHDL 2008). Hence both RTL and Verif team can add 9and debug) assertions. This is very important from a methodology standpoint of adopting ABV.
2. PSL historically has better support in Formal tools than SVA
3. PSL has some nice inheritance features that SVA (not SV-TB/class stuff) doesn’t have
4. PSL’s so called FL (Foundation Layer/language) sub-set is lot more efficient and intuitive to write succinct temporals than SEREs/sequences as in SVA (2005). Note: SVA-09 did add it and calls it LTL, but very few tools support it even today. So if you want to be productive PSL is THE way to go. See: https://www.cvcblr.com/blog/?p=689 for a small example on this.
5. PSL also has SV flavor, so learn one language, both VHDL & SV users can use it.
6. PSL works with E/Specman nicely with built-in action blocks (similar to Jim’s proposals), so this makes it even more compelling.
7. Last but not the least – it is not all that difficult to migrate from PSL to SVA (or vice versa) if one needs in the future, so get productive with PSL today and if you ever have to migrate to SVA – it is not that hard.