Open Source VHDL Verification Methodology (OSVVM) has been named the number #1 VHDL Verification Library by The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study.
While your EDA vendor may […]
In the latest release of Open Source VHDL Verification Methodology (OSVVM), all licenses for the entire OSVVM library (utility and model libraries) were updated to Apache 2.0 license. This is being done in p […]
I see that OS-VVM is using protected types internally at the quite advanced level. I have done my share of coding in VHDL but am not very familiar with this type of construct. Any suggestions how to improve my understanding?